Latency Tolerance Messaging for Low Power I/O Subsystems
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Solution Overview
Problem
Current power management in electronic devices often sacrifices performance for power optimization, limiting the ability to enter deeper low power states due to latency requirements, especially in devices connected to buses that do not support latency tolerance messaging.
Innovation Solution
The implementation of dynamic latency tolerance messaging allows device driver software to update hardware latency registers based on activity levels, enabling deeper power states by conveying latency requirements to the platform power management controller, even in devices connected to buses like SDIO and UART, which lack dynamic latency indication mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the device enters deeper low power states to optimize power consumption, then battery life is extended, but the device cannot meet latency requirements for devices connected to buses without dynamic latency indication mechanisms
Solution Approach 1:
The patent implements dynamic latency tolerance messaging that allows the device to communicate varying latency requirements to the host controller based on current activity levels. The latency tolerance value is dynamically adjusted and communicated through registers, enabling the system to enter deeper power states when latency tolerance is high and maintain shallower states when low latency is required, thus resolving the contradiction between power optimization and latency compliance
Solution Approach 2:
The patent changes the latency tolerance parameter dynamically based on device activity levels. By modifying the latency tolerance value in hardware registers and communicating it to the host controller, the system adapts its power state depth to match current performance requirements, allowing deeper power states when acceptable latency is high and preventing excessive power savings when low latency is critical
2Speed
If the device maintains shallower power states to meet latency requirements, then responsiveness is maintained, but power optimization is compromised
Solution Approach 1:
The system dynamically adjusts power state depth based on real-time latency requirements communicated through the dynamic latency tolerance messaging mechanism. When responsiveness is critical, the latency tolerance value indicates shallower power states; when responsiveness is less critical, deeper power states are permitted, thus optimizing power consumption while maintaining required responsiveness
Solution Approach 2:
By changing the latency tolerance parameter based on activity levels, the system allows shallower power states when low latency is required (maintaining responsiveness) and enables deeper power states when higher latency is acceptable (optimizing power consumption), effectively resolving the trade-off between speed and energy use
3Adaptability or versatility
If devices connected to buses without latency tolerance messaging support are used, then device compatibility is maintained, but the ability to enter deep power states is limited
Solution Approach 1:
The patent introduces an intermediary mechanism (hardware registers and latency tolerance messaging protocol) between the device and the host controller that enables dynamic latency indication even on buses that natively lack this capability. This intermediary layer translates device activity levels into latency tolerance values that the host controller can use to manage power states, thus enabling deep power states while maintaining compatibility with buses that don't natively support latency messaging
Data Source
AI summary
In at least one embodiment described herein, an apparatus is provided that can include means for communicating a latency tolerance value for a device connected to a platform from a software latency register if a software latency tolerance register mode is active. The apparatus may also include means for communicating the latency tolerance value from a hardware latency register if a host controller is active. The latency tolerance value can be sent to a power management controller. More specific examples can include means for communicating a latency tolerance value from the software latency register if the software latency tolerance register mode is not active and the host controller is not active. The apparatus can also include means for mapping a resource space in the software latency register for the device using a BIOS/platform driver. The mapping can be achieved using an advanced configuration and power interface device description.