Lateral 3D DRAM Fabrication Sequence for Thermal Reliability
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Solution Overview
Problem
The challenge in fabricating lateral 3D DRAMs is the degradation of semiconductor components during thermal processes, particularly the formation of thin film transistors, CMOS structures, capacitor bottom electrodes, and capacitors, which affects the reliability and yield of the memory devices due to the need for high-temperature processes that exceed the optimal formation temperatures of these components.
Innovation Solution
Reorganizing the fabrication process order to form the thin film transistor, capacitor bottom electrode, CMOS structure, and capacitor in a sequence that allows higher temperature processes to occur before lower temperature processes, using epitaxially grown silicon germanium and silicon layers to mitigate defects and strain, and employing a silicon wafer as a substrate for single crystal silicon growth to maintain device integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If higher temperature processes are performed first in the fabrication sequence, then manufacturing precision and reliability of thin film transistors and CMOS are improved, but device complexity and process integration difficulty increase
Solution Approach 1:
The patent performs higher temperature processes (such as silicon germanium epitaxial growth at 700-900°C) before lower temperature processes (such as capacitor dielectric deposition at 400-600°C). This preliminary action ensures that temperature-sensitive components like thin film transistors and CMOS are formed under optimal high-temperature conditions first, improving their reliability before subsequent lower-temperature layers are added.
Solution Approach 2:
The fabrication process is segmented into distinct temperature zones and sequential stages: high-temperature epitaxial growth for access devices, intermediate-temperature doping and gate formation, and low-temperature capacitor formation. This segmentation allows each component to be optimized for its specific temperature requirements while maintaining overall process integration.
2Productivity
If design rules are shrunk to increase cell density, then productivity and storage capacity are improved, but manufacturing precision and yield deteriorate due to degraded performance from high-temperature processes
Solution Approach 1:
The patent transitions from planar 2D memory architecture to vertical 3D architecture by forming silicon germanium layers horizontally and digit lines vertically. This dimensional change increases cell density without proportionally reducing feature sizes, allowing higher productivity while maintaining manufacturing precision through relaxed lateral dimensions.
Solution Approach 2:
Different regions of the memory device are formed with different thermal histories and material compositions. Access devices are formed in high-temperature epitaxial layers with specific crystal orientations, while capacitors are formed in lower-temperature dielectric layers. This local quality optimization allows each region to achieve its最佳 performance characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and yield of lateral 3D DRAMs by reducing the impact of thermal processes on component degradation, allowing for higher cell density and lower fabrication costs while maintaining capacitor characteristics.
Implementation Method 1
epitaxially grown silicon germanium and silicon layers to form horizontal access devices
Data Source
AI summary
Methods and devices for a lateral three-dimensional memory device, are described herein. One method includes forming a thin film transistor including a first thermal process having a first range of temperatures, forming a capacitor bottom electrode of a capacitor structure including a second thermal process having a second range of temperature, wherein a maximum temperature in the second range of temperatures is less than a maximum temperature in the first range of temperatures, forming a CMOS structure including a third thermal process having a third range of temperatures, wherein a maximum temperature in the third range of temperatures is less than a maximum temperature in the second range of temperatures, and forming at least one other part of the capacitor structure.