Lateral Bipolar Transistor ESD Protection for Passive RF Circuits
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Solution Overview
Problem
Existing ESD protection circuits for high frequency differential signals, particularly in passive RF microelectronic circuits, face issues with high parasitic capacitance, partial triggering during normal operation due to signal rate of rise, and requirement for defined polarity, making them unsuitable for applications like RFID tags and contactless smart cards.
Innovation Solution
A lateral bipolar transistor ESD protection circuit with an n-type emitter and collector in a p-well region, isolated in an n-well within a p-type substrate, which introduces minimal parasitic capacitance and leakage during normal operation and triggers to discharge ESD events based on voltage levels, suitable for passive RF circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ggNMOS-based ESD protection circuits are used, then ESD protection is provided, but parasitic capacitance increases causing power loss
Solution Approach 1:
The patent changes the triggering parameter from signal rate of rise (dg/dt) to voltage threshold (Vth). By using a voltage-triggered mechanism instead of rate-of-rise triggering, the ESD protection circuit maintains low parasitic capacitance while providing effective protection, eliminating the power loss issue associated with ggNMOS circuits.
2Reliability
If ggNMOS-based ESD protection circuits are used, then ESD protection is provided, but the circuit is partially triggered during normal RF operation due to signal rate of rise
Solution Approach 1:
The patent changes the triggering parameter from signal rate of rise (dg/dt) to voltage threshold (Vth). This voltage-triggered mechanism distinguishes between normal RF signals (which do not exceed Vth) and ESD events (which exceed Vth), preventing false triggering during normal operation and eliminating signal loss.
3Reliability
If ggNMOS-based ESD protection circuits are used, then ESD protection is provided, but defined polarity is required making them unsuitable for passive RF devices
Solution Approach 1:
The patent creates a universal ESD protection circuit based on voltage-triggered diodes that functions independently of signal polarity. The circuit can protect both single-ended and differential signals, and is compatible with passive RF devices that lack external power supplies, as it triggers solely on voltage magnitude exceeding Vth regardless of polarity.
4Loss of energy
If diode-based ESD protection circuits are used, then parasitic capacitance is reduced, but defined voltage levels relative to external power supplies are required
Solution Approach 1:
The patent creates a universal ESD protection circuit using voltage-triggered diodes that does not require external power supplies. The circuit triggers purely on voltage magnitude exceeding a threshold, making it compatible with passive RF devices while maintaining low parasitic capacitance characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively protects passive RF microelectronic circuits from ESD events with minimal power loss and no polarity constraints, ensuring reliable operation during high frequency differential signal handling.
Implementation Method 1
ESD events occur when a large current pulse is discharged through a microelectronic circuit
Implementation Method 2
one of the triggering mechanisms in a ggNMOS-based ESD protection circuit during an ESD event is the signal rate of rise
Data Source
AI summary
A lateral bipolar transistor is used to protect a passive radio frequency (RF) microelectronic circuit during electrostatic discharge (ESD) events. The microelectronic circuit receives a high frequency differential input signal across first and second pads. The lateral bipolar transistor includes an n-type emitter coupled to the first pad and an n-type collector coupled to the second pad. The emitter and collector are located in a p-well, which forms the base of the transistor. The p-well is located in an isolating n-well, which in turn, is located in a p-type substrate. The n-well is coupled to receive the VDD supply voltage and the p-substrate is coupled to a VSS reference voltage. A dielectric region can be located between the emitter and collector (in the p-well).