Lateral Bipolar Transistor Integrated ESD Device in Triple Well
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Solution Overview
Problem
Existing integrated circuit designs face challenges in reducing the size of electrostatic discharge (ESD) protection devices without compromising their protection capabilities, as they occupy a large percentage of the I/O area, making it difficult to increase the number of I/O pins while maintaining sufficient ESD protection.
Innovation Solution
The integration of a lateral bipolar transistor within a MOSFET, specifically using a triple well structure with isolated wells and diodes, reduces the trigger voltage, increases failure current, and decreases on-resistance, allowing for a smaller ESD protection device area while maintaining or exceeding protection capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of ESD protection devices is reduced, then the number of I/O pins can be increased, but the protection capability deteriorates
Solution Approach 1:
The patent combines a lateral bipolar transistor with a MOSFET into an integrated structure, where the bipolar transistor's collector is connected to the MOSFET's drain and the bipolar's emitter connects to the I/O pad. This merging allows the compact combined structure to provide both ESD protection and I/O functionality, enabling increased I/O pin count while maintaining protection capability through the synergistic operation of the two transistor types.
Solution Approach 2:
The patent modifies key ESD device parameters by integrating the lateral bipolar transistor, which changes the trigger voltage, failure current, and on-resistance characteristics. The bipolar transistor's presence alters the electrical parameters to achieve lower trigger voltage and higher failure current, allowing reduced device area while maintaining or improving ESD protection performance.
2Area of stationary object
If the area of ESD protection devices is reduced, then more I/O pins can be accommodated, but the failure current decreases
Solution Approach 1:
The lateral bipolar transistor is merged with the MOSFET such that the bipolar's collector connects to the MOSFET's drain region. This integration allows the bipolar transistor to contribute its high current capability to the ESD protection path, enabling the reduced-area device to maintain high failure current through the combined structure rather than relying solely on MOSFET dimensions.
Solution Approach 2:
The integration of the lateral bipolar transistor fundamentally changes the failure current parameter by introducing an additional current path through the bipolar device. The bipolar transistor's higher current density capability compensates for the reduced physical area, achieving increased failure current despite smaller device footprint.
3Area of stationary object
If the area of ESD protection devices is reduced, then more I/O pins can be accommodated, but the on-resistance increases
Solution Approach 1:
The lateral bipolar transistor is integrated with the MOSFET such that during normal operation, the bipolar device provides an additional parallel conduction path. This merging of conduction paths reduces the overall on-resistance of the ESD protection device, compensating for the reduced physical area and enabling lower on-resistance in the compact structure.
4Area of moving object
If the size of ESD protection devices is reduced, then the I/O area increases, but the trigger voltage increases
Solution Approach 1:
The lateral bipolar transistor integration changes the trigger voltage parameter by introducing an alternative triggering mechanism through the bipolar device's base-emitter junction. The bipolar transistor can be triggered at lower voltages through substrate injection or direct base connection, enabling the reduced-size device to achieve lower trigger voltage compared to a scaled-down MOSFET alone.
Data Source
AI summary
A structure and method of fabricating electrostatic discharge (EDS) circuitry in an integrated circuit chip by integrating a lateral bipolar, either a p-n-p with a NMOSFET or a n-p-n with a PMOSFET within a triple well. The lateral bipolar preferably includes diodes at the I/O and/or the VDDs of the circuitry.