Lateral BJT Layout With Base Under Gate for Compact Symmetry

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Solution Overview

Problem

The challenge in fabricating compact lateral Bipolar Junction Transistors (BJTs) is due to their larger natural area occupation, misalignment of N and P implants, and complexity in miniaturization processes such as self-alignment techniques and alignment with Shallow Trench Isolation (STI) and Resist Protection Oxide (RPO) processes.

Innovation Solution

The solution involves designing lateral BJTs with the base located underneath the gate, using symmetric layouts such as T, Pi, or H shaped gates to reduce gate and base resistances, and employing compact layouts with common base connections to minimize device size and mismatch sensitivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If conventional lateral BJT layout is used, then device functionality is achieved, but device area is large

Engineering Contradiction:
Improvedevice areaVSAvoiddevice functionality
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The patent transitions from a conventional lateral layout to a vertical-under-gate layout where the base region is positioned underneath the gate structure. This dimensional reorganization allows the emitter and collector to be laterally adjacent while the base extends vertically underneath the gate, significantly reducing the device footprint while maintaining proper transistor functionality through controlled doping profiles.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If self-alignment techniques are used for miniaturization, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improvealignment precisionVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent employs preliminary doping actions where the base region is doped underneath the gate structure before final gate formation. This preliminary action establishes precise alignment boundaries that guide subsequent processing steps, eliminating the need for complex self-alignment techniques while maintaining high manufacturing precision through pre-defined doping profiles and mask patterns.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If symmetric layout is used, then variability is reduced, but manufacturing complexity increases

Engineering Contradiction:
Improvedevice variabilityVSAvoidmanufacturing ease
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent employs asymmetric doping profiles and asymmetric gate electrode configurations relative to the base region. The base is positioned underneath the gate with asymmetric extension on one side, and the emitter-collector spacing is deliberately asymmetric. This controlled asymmetry simplifies the manufacturing process by reducing alignment constraints while maintaining low variability through precise doping control and geometric optimization.

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS20250093211A1Lateral bipolar junction transistor device and method of forming same
Publication Date: 2025.03.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250093211A1 patent drawing
  • US20250093211A1 patent drawing
  • US20250093211A1 patent drawing

AI summary

A lateral-bipolar junction transistor (BJT) including a semiconductor substrate, an insulator region disposed on the semiconductor substrate, and a well region comprising a well semiconductor of a first conductivity type disposed over the insulator region. An emitter region of a second conductivity type is disposed in the well region, and at least one collector region of a second conductivity type is disposed in the well region. A T shaped, Pi shaped or H shaped gate and gate oxide layer includes a gate portion extending between the emitter region and one or more collector regions, and a base is disposed underneath the gate portion. In other embodiments, a metal oxide semiconductor (MOS) transistor-based circuit similarly employs a compact Pi or H shaped gate and gate oxide layer.