Lateral BJT Stress Layer Layout for SOI Frequency Retention

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Solution Overview

Problem

Advanced silicon-on-insulator (SOI) processing technology platforms struggle to integrate vertical bipolar junction transistors (BJTs) effectively, limiting their use in high-performance applications due to orientation constraints and performance impacts on cut-off frequency and beta cut-off frequency.

Innovation Solution

A semiconductor structure with a lateral bipolar junction transistor (BJT) is integrated into the SOI platform, featuring a dielectric stress layer that partially covers the transistor, enhancing charge carrier mobility, and optionally configured as a lateral heterojunction bipolar transistor (HBT) with different semiconductor materials for the base, collector, and emitter.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If vertical bipolar junction transistors are integrated into SOI platforms, then BJT functionality is achieved, but performance characteristics such as cut-off frequency and beta cut-off frequency deteriorate due to orientation constraints

Engineering Contradiction:

ImproveBJT functionalityVSAvoidcut-off frequency

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The patent inverts the conventional vertical BJT orientation by implementing a lateral BJT structure where the collector, base, and emitter are arranged horizontally rather than vertically. This inversion allows the BJT to function effectively within the SOI platform while maintaining or improving performance characteristics like cut-off frequency and beta cut-off frequency.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent transitions from a vertical three-dimensional arrangement to a lateral two-dimensional arrangement within the semiconductor layer. By changing the spatial dimension from vertical stacking to lateral positioning, the BJT achieves better integration with the SOI platform and improved electrical performance without compromising functionality.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Speed

If a dielectric stress layer is added to enhance charge carrier mobility, then performance characteristics improve, but device complexity increases

Engineering Contradiction:

Improvecharge carrier mobilityVSAvoidstructure complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The dielectric stress layer is applied selectively to specific regions of the lateral BJT structure rather than uniformly across the entire device. This localized application enhances charge carrier mobility in critical areas while minimizing the overall increase in device complexity and maintaining compatibility with standard SOI processing techniques.

Inventive Principle:

Principle #3Local quality

3Adaptability or versatility

If lateral BJT configuration is implemented, then integration into SOI platform is improved, but manufacturing precision requirements increase

Engineering Contradiction:

Improveintegration capabilityVSAvoidlateral alignment precision

Core Design Contradiction:

Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The lateral BJT structure is designed with pre-defined alignment features and standardized geometries that facilitate precise positioning during manufacturing. By establishing the lateral configuration early in the design phase with built-in alignment references, the patent enables better integration into the SOI platform while managing manufacturing precision requirements through proactive design considerations.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration maintains or improves performance characteristics such as cut-off frequency and beta cut-off frequency, enabling better integration and performance of BJTs in SOI platforms, particularly through enhanced charge carrier mobility and strain application.

Implementation Method 1

a dielectric stress layer that only partially covers the lateral BJT with one end being above the lateral BJT between the collector and the emitter

Methodology Applied

Scientific EffectStrain: Deformation

Data Source

PatentUS11837653B2Lateral bipolar junction transistor including a stress layer and method

Publication Date: 2023.12.05 GLOBALFOUNDRIES US INC

AI summary

Disclosed is a semiconductor structure with a lateral bipolar junction transistor (BJT). This semiconductor structure can be readily integrated into advanced silicon-on-insulator (SOI) technology platforms. Furthermore, to maintain or improve upon performance characteristics (e.g., cut-off frequency (fT)/maximum oscillation frequency (fmax) and beta cut-off frequency) that would otherwise be negatively impacted due to changing of the orientation of the BJT from vertical to lateral, the semiconductor structure can further include a dielectric stress layer (e.g., a tensilely strained layer in the case of an NPN-type transistor or a compressively strained layer in the case of a PNP-type transistor) partially covering the lateral BJT for charge carrier mobility enhancement and the lateral BJT can be configured as a lateral heterojunction bipolar transistor (HBT). Also disclosed is a method for forming the semiconductor structure.