Semiconductor Package Layout With Lateral Bridge Die for Thinner HBM
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving reduced thickness, efficient heat dissipation, and high-performance connectivity, particularly in high bandwidth memory (HBM) applications, due to the positioning of bridge dies below logic dies, which increases package thickness and heat generation, affecting memory die performance.
Innovation Solution
A semiconductor package design where the bridge die is positioned alongside the memory stack and logic die, with advanced through-vias and hybrid bonding for efficient connections, and encapsulation materials for protection and electrical pathways, allowing for reduced thickness and improved heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the bridge die is positioned below the logic die, then the connectivity between memory and logic is achieved, but the package thickness increases and heat dissipation efficiency deteriorates
Solution Approach 1:
The bridge die is repositioned from a vertical stacking arrangement (below logic die) to a lateral arrangement (alongside memory stack and logic die), changing the spatial dimension of connection. This dimensional shift reduces package thickness while maintaining connectivity through lateral routing via via pads and conductive pathways.
Solution Approach 2:
The package structure is segmented into distinct functional regions: memory stack region, logic die region, and bridge die region, each positioned independently on the package substrate. This segmentation allows optimized heat dissipation pathways for each component while maintaining compact overall dimensions.
2Reliability
If the bridge die is positioned below the logic die, then the electrical connection is established, but the heat generation affects memory die performance
Solution Approach 1:
Each component (memory stack, logic die, bridge die) is positioned with dedicated heat dissipation pathways and spacing. The bridge die is laterally positioned to create separate thermal zones, allowing localized heat management where each component's heat can be dissipated independently without affecting adjacent components' performance.
3Reliability
If through-vias and hybrid bonding are used for connections, then the connectivity performance is improved, but the manufacturing complexity increases
Solution Approach 1:
Through-vias are pre-formed in the package substrate before component placement, and hybrid bonding interfaces are prepared in advance on both the bridge die and memory stack. This preliminary preparation of connection pathways simplifies the final assembly process by reducing on-the-fly alignment and bonding complexity.
Data Source
AI summary
A semiconductor package includes a wiring structure. A buffer die is disposed on the wiring structure. A logic die is disposed alongside the buffer die on the wiring structure. A first encapsulating material covers at least a portion of each of the buffer die and the logic die. A memory stack is disposed on the buffer die and is electrically connected to the buffer die. A bridge die is disposed so as to extend over at least a portion of each of the buffer die and the logic die, and is electrically connected to each of the buffer die and the logic die. A second encapsulating material covers at least a portion of each of the memory stack and the bridge die. The buffer die and the logic die are disposed at a level that is between those of the wiring structure and the bridge die.