3D Semiconductor Device With Lateral Channel And Self-Aligned Gate
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Solution Overview
Problem
Current methods for manufacturing 3D resistance variable memory devices with vertical pillar structures face challenges due to complex fabrication processes and misalignment issues, which affect integration density and reliability.
Innovation Solution
A method involving the formation of a semiconductor device with a horizontal channel structure, where a common source node and gate are self-aligned, and resistance variable material layers are formed on heating electrodes, improving aspect ratio and integration density while reducing alignment defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a vertical pillar structure is used for manufacturing switching devices, then three-dimensional integration is achieved, but the fabrication process becomes complex and the aspect ratio increases
Solution Approach 1:
The patent inverts the conventional vertical pillar structure by adopting a horizontal channel structure where the channel extends laterally rather than vertically. This inversion maintains three-dimensional integration capabilities while simplifying the fabrication process and reducing aspect ratio requirements, as the channel is formed in a plane parallel to the substrate rather than as a tall vertical structure
2Manufacturing precision
If multiple alignment processes are performed to align channel with source node and gate with channel, then precise positioning is achieved, but misalignment defects occur
Solution Approach 1:
The patent implements self-aligned fabrication where the horizontal channel structure automatically defines the positioning of source and drain regions through its geometric configuration. The channel's lateral extension from the source node region inherently guides the placement of subsequent structures, eliminating the need for separate alignment processes and preventing misalignment defects
Solution Approach 2:
The horizontal channel structure is formed in advance as a reference feature that pre-determines the positions of source and drain regions. This preliminary formation of the channel structure serves as a template for subsequent fabrication steps, ensuring precise positioning without requiring additional alignment operations
Data Source
AI summary
A 3D semiconductor device and a method of manufacturing the same are provided. The method includes forming a first semiconductor layer including a common source node on a semiconductor substrate, forming a transistor region on the first semiconductor layer, wherein the transistor region includes a horizontal channel region substantially parallel to a surface of the semiconductor substrate, and source and drain regions branched from the horizontal channel region to a direction substantially perpendicular to the surface of the semiconductor substrate, processing the first semiconductor layer to locate the common source node corresponding to the source region, forming a gate in a space between the source region and the drain region, forming heating electrodes on the source region and the drain region, and forming resistance variable material layers on the exposed heating electrodes.