Lateral Control Gate Memory Structure for CMOS Integration
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Solution Overview
Problem
Conventional flash memory cell manufacturing processes are complex and difficult to integrate with logic circuit fabrication due to the need for additional polysilicon processes, complicating the integration and increasing the time and steps required.
Innovation Solution
A memory structure with a lateral side control gate is fabricated using the same process as a typical logic circuit transistor, where the control gate is disposed on the lateral sides of the floating gate, reducing the need for separate polysilicon processes and utilizing conductive plugs as control gates, which are fabricated during metal interconnection, and employing a dielectric layer with increased lateral coupling area to enhance capacitance and operating efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flash memory cell is fabricated with two stacked polysilicon layers for control gate and floating gate, then the memory cell can store data, but the manufacturing process becomes more complicated and requires separate fabrication from logic circuits
Solution Approach 1:
The patent merges the memory cell fabrication process with the standard logic circuit CMOS fabrication process. The control gate and floating gate are formed using the same polysilicon layers and processing steps as the logic circuit transistors, eliminating the need for separate memory fabrication processes while maintaining data storage functionality.
Solution Approach 2:
The polysilicon layers serve dual purposes: they form the control gates for both the logic circuit transistors and the memory cells, and they also form the floating gates for data storage in the memory cells. This multi-functional use of the same structures simplifies the overall manufacturing process.
2Reliability
If conventional flash memory cell uses stacked polysilicon layers for control gate and floating gate, then the memory cell can function, but additional polysilicon processes are required increasing manufacturing steps and time
Solution Approach 1:
The patent combines the memory cell formation with the standard CMOS fabrication sequence. The same polysilicon deposition, doping, and patterning steps that create logic circuit transistors also create the memory cell structures, eliminating redundant processing steps and improving manufacturing efficiency.
Solution Approach 2:
The control gate and floating gate structures are formed during the preliminary stages of the CMOS fabrication process, before the final metal interconnection layers are deposited. This preliminary formation of memory structures allows them to be integrated into the standard fabrication flow without requiring additional processing steps after the main CMOS process is complete.
3Ease of manufacture
If conventional flash memory requires separate fabrication process, then memory cell can be manufactured, but the time and steps of manufacturing process are increased
Solution Approach 1:
The patent merges the memory cell fabrication into the standard logic circuit fabrication process flow. Both memory cells and logic circuits are manufactured simultaneously using the same process steps, eliminating the need for separate fabrication lines and reducing overall manufacturing cycle time.
Solution Approach 2:
The fabrication process is designed to be universal, producing both logic circuit transistors and memory cells using the same equipment and process parameters. This multi-functional process reduces the need for specialized processing steps and accelerates the overall manufacturing cycle.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces the number of photo masks and photolithographic steps, and increases the operating speed and efficiency of the memory device by enhancing the gate coupling ratio.
Implementation Method 1
employing a dielectric layer with increased lateral coupling area to enhance capacitance and operating efficiency
Data Source
AI summary
A memory structure includes a substrate, a source region, a drain region, a gate insulating layer, a floating gate and a control gate. The substrate has a surface and a well extended from the surface to the interior of the substrate. The source region and the drain region are formed in the well and a channel region is formed between the source region and the drain region. The gate insulating layer is formed on the surface of the substrate between the source region and the drain region and covers the channel region. The floating gate disposed on the gate insulating layer to store a bit data. The control gate is disposed near lateral sides of the floating gate.