Lateral Coupling Capacitor for Embedded Nonvolatile Memory
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Solution Overview
Problem
The complexity of manufacturing nonvolatile memory devices with stacked gate structures on the same substrate as logic devices complicates the fabrication process, leading to a need for a simpler embedded nonvolatile memory device structure that can be integrated with CMOS processes.
Innovation Solution
A nonvolatile memory device with a lateral coupling structure, featuring a selection gate electrode layer, a dielectric layer, and a floating gate electrode layer arranged at the same level to form a lateral coupling capacitor, allowing for a single poly nonvolatile memory device with a single gate structure that simplifies the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a stacked gate structure is used for nonvolatile memory devices, then data storage capability is improved, but manufacturing complexity increases when integrated with logic devices
Solution Approach 1:
The patent transitions from a vertical stacked gate structure to a lateral coupling structure where the selection gate and floating gate are arranged side-by-side in the same plane. This dimensional change eliminates the need for complex vertical stacking processes while maintaining the essential capacitive coupling function for data storage, thereby reducing manufacturing complexity when integrating with CMOS logic devices.
Solution Approach 2:
The lateral coupling structure uses a single poly-silicon layer to form both the selection gate electrode and the floating gate electrode, allowing the same material layer to serve multiple functions. This universal approach enables nonvolatile memory devices to be fabricated using standard CMOS single-poly processes, making the structure compatible with logic device manufacturing and eliminating the need for separate stacked gate fabrication processes.
2Ease of manufacture
If a single poly nonvolatile memory device with single gate structure is used, then ease of manufacture is improved, but device functionality must be maintained
Solution Approach 1:
The single poly-silicon gate layer is segmented into two distinct functional regions: the selection gate electrode layer and the floating gate electrode layer. This segmentation is achieved through selective masking and etching processes that divide the continuous poly layer into separate functional zones, allowing each region to perform its specific function while being fabricated from the same material layer.
Solution Approach 2:
A dielectric layer is introduced as an intermediary between the selection gate electrode layer and the floating gate electrode layer. This dielectric layer acts as a mediator that provides electrical isolation between the two gates while allowing capacitive coupling through the tunnel insulation layer, thereby maintaining the essential functionality of the nonvolatile memory device despite using a simplified single-poly structure.
3Productivity
If logic devices and nonvolatile memory devices are fabricated in the same process step, then productivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses the same poly-silicon material and identical fabrication processes for both the logic device transistors and the nonvolatile memory device gates. This homogeneous approach ensures that both device types are fabricated simultaneously using standard CMOS single-poly processes, achieving process compatibility and high integration efficiency without requiring separate fabrication lines or additional processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the efficient integration of nonvolatile memory devices with logic devices on the same substrate, reducing manufacturing complexity and facilitating the production of system-on-chip (SOC) devices by using a lateral coupling structure that effectively programs and erases data.
Implementation Method 1
The selection gate electrode layer, the dielectric layer, and the floating gate electrode layer are located substantially at the same level and, in combination, form a lateral coupling capacitor
Data Source
AI summary
A nonvolatile memory cell includes an active region extending in a first direction, a selection gate electrode layer intersecting the active region and extending in a second direction, a floating gate electrode layer intersecting the active region, extending in the second direction, wherein the floating gate electrode layer extends in parallel to the selection gate electrode layer and is separated from the selection gate electrode layer, and a dielectric layer disposed between the selection gate electrode layer and the floating gate electrode layer. The selection gate electrode layer, the dielectric layer, and the floating gate electrode layer are located substantially at the same level and, in combination, form a lateral coupling capacitor, and a first end portion of the floating gate electrode layer overlaps the active region.