Lateral Coupling NVM Cells for Single-Layer Gate Integration
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Solution Overview
Problem
The integration of nonvolatile memory (NVM) devices with logic devices in system-on-chip (SOC) products is challenging due to the mismatch in process technologies, as NVM devices require a stack gate structure while logic devices use a single gate structure, leading to complex fabrication processes.
Innovation Solution
The implementation of nonvolatile memory cells with a lateral coupling structure, including a selection transistor, a cell transistor with a floating gate, and coupling capacitors, which allows for a single-layered gate structure compatible with CMOS circuits, enabling simpler fabrication and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If NVM devices use a stack gate structure to achieve nonvolatile memory functionality, then data retention capability is improved, but fabrication process complexity increases due to incompatibility with logic device processes
Solution Approach 1:
The memory cell is divided into two separate transistors: a selection transistor with a single-layer gate for compatibility with logic device fabrication, and a cell transistor with a stacked gate structure (control gate and floating gate) for nonvolatile memory functionality. This segmentation allows each transistor to be optimized for its specific function while using compatible fabrication processes.
Solution Approach 2:
The selection transistor serves dual purposes: it acts as a standard single-gate transistor compatible with CMOS logic device fabrication processes, and simultaneously provides the selection function for the memory cell. This universality allows the same fabrication process to manufacture both logic devices and memory devices.
2Ease of manufacture
If NVM devices use a single-layered gate structure to simplify fabrication and improve compatibility with CMOS circuits, then ease of manufacture is improved, but data retention capability deteriorates compared to stack gate structures
Solution Approach 1:
The memory functionality is segmented between two transistors: the selection transistor uses a single-layer gate for fabrication compatibility, while the cell transistor uses a stacked gate structure with a floating gate to provide the necessary data retention capability for nonvolatile memory operation.
Solution Approach 2:
A coupling capacitor is introduced as an intermediary element to connect the selection gate to the floating gate of the cell transistor. This capacitor enables the transfer of charge between the selection gate and floating gate, allowing the single-layer gate selection transistor to control the stacked gate cell transistor and achieve both fabrication compatibility and data retention.
3Ease of manufacture
If a lateral coupling structure with coupling capacitors is implemented to enable single-layered gate compatibility, then ease of manufacture is improved, but device structure complexity increases
Solution Approach 1:
The coupling capacitor is integrated into the existing transistor structure by forming it using the same gate electrode and dielectric layer that form the selection gate. This merging approach allows the capacitor to be created during the standard transistor fabrication process without requiring separate capacitor fabrication steps, thereby reducing overall manufacturing complexity despite the additional functional element.
Solution Approach 2:
The gate structure of the selection transistor serves multiple functions: it acts as the control gate for the selection transistor, forms one plate of the coupling capacitor, and provides the lateral coupling mechanism to the floating gate. This multi-functionality reduces the need for separate dedicated capacitor structures and simplifies the overall fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution facilitates the integration of NVM devices into SOC products by reducing the complexity of fabrication processes and enhancing the performance of NVM cells through optimized coupling mechanisms for programming, erasure, and read operations.
Implementation Method 1
a first coupling capacitor disposed in a first connection line coupled between the word line and the floating gate, and a P-N diode and a second coupling capacitor disposed in series in a second connection line coupled between the word line and the floating gate
Implementation Method 2
An anode and a cathode of the P-N diode are coupled to the second coupling capacitor and the word line, respectively
Data Source
AI summary
A nonvolatile memory (NVM) cell includes a selection transistor configured to have a selection gate terminal coupled to a word line and a source terminal coupled to a source line, a cell transistor configured to have a floating gate electrically isolated, a drain terminal coupled to a bit line and sharing a junction terminal with the selection transistor, a first coupling capacitor disposed in a first connection line coupled between the word line and the floating gate, and a P-N diode and a second coupling capacitor disposed in series in a second connection line coupled between the word line and the floating gate. An anode and a cathode of the P-N diode are coupled to the second coupling capacitor and the word line, respectively. The first and second connection lines are coupled in parallel between the word line and the floating gate.