Chiplet-in-Cavity Wafer Assembly With Lateral Dielectric Bonding
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Solution Overview
Problem
There is a need for an electronic assembly that integrates pre-fabricated interconnects and integrated circuitry on a host wafer with active chiplets, allowing for faster and cost-effective manufacturing of microwave or RF integrated circuits by decoupling the fabrication of active and passive circuits.
Innovation Solution
The integration of chiplets with active circuits into the host wafer cavities using lateral dielectric material, which forms a mechanical and chemical bond between the chiplets and the wafer, enabling efficient interconnect routing and heat transfer while allowing for different semiconductor technologies to be combined.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If microelectronic circuits are fabricated separately and assembled together, then improved fabrication yields and circuit performance are achieved, but manufacturing complexity and assembly process difficulty increase
Solution Approach 1:
The invention divides the final circuit into separate functional modules (active chiplets and passive circuits) that are fabricated independently on different wafers using optimized processes for each type, then integrates them through wafer-level packaging. This segmentation enables each module to be manufactured with high yield using specialized processes while maintaining overall system performance.
Solution Approach 2:
The invention merges multiple separately fabricated wafers (active chiplet wafer and passive circuit wafer) into a single integrated package at the wafer level. This combining approach maintains the benefits of separate fabrication (yield improvement, process optimization) while achieving a compact, high-performance final product with reduced assembly complexity compared to discrete component assembly.
2Reliability
If different semiconductor technologies are combined in a single final component, then circuit performance is improved, but manufacturing cost and process difficulty increase
Solution Approach 1:
The invention segments the circuit into active devices (requiring specialized semiconductor processes) and passive circuits (suitable for standard PCB fabrication), allowing each to be manufactured using the most cost-effective and technologically appropriate process for its specific requirements, thereby reducing overall manufacturing cost while maintaining high performance.
Solution Approach 2:
The wafer-level packaging platform provides a universal integration architecture that can accommodate different semiconductor technologies (GaN, silicon, etc.) and circuit types (active and passive) in a single standardized package format, enabling cost-effective multi-technology integration without requiring separate complex assembly lines for each technology combination.
3Ease of manufacture
If active devices and passive circuits are fabricated together on the same wafer, then manufacturing process is simplified, but fabrication yield and cost-effectiveness decrease
Solution Approach 1:
The invention segments the fabrication process into separate stages for active devices and passive circuits, allowing each to be optimized independently. Active chiplets are fabricated using specialized semiconductor processes on dedicated wafers, while passive circuits are fabricated using standard PCB techniques on separate wafers, maximizing manufacturing efficiency for each type before integration at the wafer-level packaging stage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach facilitates faster and more cost-effective manufacturing of high-performance RF ICs by integrating chiplets with different semiconductor technologies, such as GaN and silicon-based circuits, while maintaining high manufacturing yields and scalability.
Implementation Method 1
lateral dielectric material, which forms a mechanical and chemical bond between the chiplets and the wafer
Implementation Method 2
lateral dielectric material, which forms a mechanical and chemical bond between the chiplets and the wafer
Implementation Method 3
enabling efficient interconnect routing and heat transfer
Data Source
AI summary
An electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. Chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. A lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.