Lateral Dielectric Thinning for IC Parasitic Noise Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In advanced analog and RF ICs, metal-to-polysilicon capacitors with blanket capacitor dielectric layers over the entire die area lead to lower voltage thresholds for parasitic field oxide transistors and increased noise, necessitating the partial etching of the capacitor dielectric layer to avoid transistor activation and leakage.
Innovation Solution
A method involving the partial etching of the capacitor dielectric layer laterally to the metal-to-polysilicon capacitor, using a combination of dry and wet etching techniques to thin the dielectric layer to 5-50% of its original thickness, allowing independent integration and contact formation without impacting front-end-of-line circuitry, and incorporating a charge trapping layer like silicon nitride or oxynitride with low hydrogen content.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the capacitor dielectric layer is maintained over the entire die area, then the capacitance density is increased, but the voltage threshold for parasitic field oxide transistors is reduced and noise increases
Solution Approach 1:
The capacitor dielectric layer is selectively removed in lateral regions adjacent to the capacitor while maintaining the full thickness over the capacitor structure itself. This creates different dielectric thicknesses in different locations: thin in lateral regions to prevent parasitic transistor activation, and thick over the capacitor to maintain capacitance density. The hard mask layer defines the boundary where this local quality change occurs.
2Object-affected harmful factors
If the capacitor dielectric layer is partially etched in lateral regions, then parasitic transistor activation is reduced and noise is minimized, but the manufacturing process complexity increases
Solution Approach 1:
A hard mask layer is deposited over the top plate before the dielectric thinning process. This preliminary action protects the capacitor structure during subsequent etching operations and defines the precise boundary for dielectric removal. The hard mask enables selective etching of lateral region dielectric while preserving the capacitor dielectric integrity.
Solution Approach 2:
The hard mask layer serves as an intermediary protective layer during the dielectric thinning process. It mediates between the etching process and the capacitor structure, allowing selective removal of lateral dielectric while protecting the capacitor dielectric. The hard mask is temporarily introduced and then removed after serving its protective function.
3Ease of manufacture
If the capacitor dielectric is thinned in lateral regions, then independent integration and contact formation is enabled, but the capacitor dielectric integrity may be compromised
Solution Approach 1:
The dielectric thinning is applied locally only in lateral regions where contact formation is needed, while the full-thickness dielectric is maintained over the capacitor structure. This local differentiation enables independent contact formation in lateral regions without compromising the dielectric integrity over the capacitor, where the full thickness provides adequate protection.
Solution Approach 2:
The hard mask layer acts as an intermediary that enables precise control during the dielectric thinning process. It protects the capacitor dielectric from over-etching while allowing controlled thinning in lateral regions. This intermediary layer ensures that the dielectric integrity over the capacitor is maintained even as lateral regions are thinned for contact access.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic field oxide transistor activation, minimizes noise, and maintains capacitance performance by recovering voltage thresholds and reducing CMOS noise, while ensuring the integrity of the capacitor and contact resistance.
Implementation Method 1
using a combination of dry and wet etching techniques to thin the dielectric layer
Implementation Method 2
using a combination of dry and wet etching techniques to thin the dielectric layer
Implementation Method 3
incorporating a charge trapping layer like silicon nitride or oxynitride with low hydrogen content
Data Source
AI summary
An integrated circuit (IC) includes a semiconductor surface layer on a substrate including functional circuitry having circuit elements configured together with a metal-to-polysilicon capacitor on the semiconductor surface layer for realizing at least one circuit function. The metal-to-polysilicon capacitor includes a bottom plate including polysilicon, a capacitor dielectric including at least one capacitor dielectric layer on the bottom plate, a top plate on the capacitor dielectric, and contacts through a pre-metal dielectric layer that contact the top plate and contact the bottom plate. In lateral regions relative to the capacitor the capacitor dielectric layer has a thickness in a range between about 5% and about 50% of a thickness of the capacitor dielectric of the metal-to-polysilicon capacitor.