Lateral Diffused Field Effect Transistor Trench Isolation
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to efficiently form laterally diffused field effect transistors (LDFETs) with deep well regions for high power/high voltage applications while maintaining the complexity and cost efficiency of small signal transistor processes, especially as transistor dimensions scale down, requiring effective isolation and reduced parasitic capacitance.
Innovation Solution
The solution involves forming well regions with specific conductivity types and trench isolation regions that extend into the well regions, allowing current paths adjacent to the sidewalls of the trench isolation regions, eliminating the need for deep dopant implantations and enabling efficient isolation of the drain region without additional process complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep well regions are formed for high power/high voltage transistor isolation, then reliable current isolation is achieved, but process complexity and manufacturing cost increase due to additional deep dopant implantation steps
Solution Approach 1:
The patent extracts the deep well formation step from the LDFET manufacturing process by using a shared well structure that is formed independently of the transistor-specific processing. The deep N-well is created as a separate, pre-formed structure that provides isolation without requiring additional implantation steps specific to each transistor type, thereby reducing process complexity while maintaining isolation reliability.
Solution Approach 2:
The shared deep N-well structure serves multiple functions simultaneously: it provides electrical isolation for high power transistor drain regions, acts as a common substrate for both small signal and power transistors, and eliminates the need for separate deep well formation processes for different transistor types. This multi-functionality reduces overall process complexity while maintaining reliable isolation.
2Productivity
If transistor dimensions are reduced to achieve high packing density, then more transistor elements can be implemented, but additional deep well processes become necessary increasing manufacturing cost
Solution Approach 1:
The patent merges the well structure formation into a shared infrastructure that supports both small signal transistors and LDFETs at scaled dimensions. By combining the deep well formation into a single process step that serves multiple transistor types and densities, the manufacturing cost per transistor is reduced while enabling high packing density through efficient space utilization.
Data Source
AI summary
An LDFET may be formed on the basis of manufacturing platforms designed for forming sophisticated small signal transistor elements. To this end, sidewall areas of trench isolation regions laterally positioned within the drift region may be used as current paths, thereby achieving increased design flexibility, since efficient current paths may still be established, even if the trench isolation regions have to extend into the substrate material due to design criteria determined by the sophisticated small signal transistor elements. In some illustrative embodiments, isolation of P-LDFETs with respect to the P-substrate may be accomplished without requiring a deep well implantation.