Lateral Diode Layout for Backside Power Rail Current Continuity
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Solution Overview
Problem
Conventional diodes in backside power delivery designs for semiconductor wafers face issues with current path disruption due to thinning, as N-well/P-well connections are cut off during polishing, disrupting current flow between different operation domains.
Innovation Solution
A semiconductor structure with metal gate structures and S/D contacts on N-well or P-well, including a dummy gate structure as an oxide definition region, ensures a directional current path by forming connections through epitaxial layers, maintaining current flow even during substrate thinning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the wafer is thinned by polish for backside power delivery, then the power delivery efficiency is improved, but the N-well/P-well connections are cut off causing current path disruption
Solution Approach 1:
The patent transitions from a vertical current path (through thinned substrate) to a lateral current path (along the epitaxial layers). By configuring the diode structure with P+ and N+ epitaxial regions extending laterally and forming current paths in the X-direction, the design eliminates dependence on vertical substrate thickness, enabling backside power delivery without compromising current path integrity.
2Ease of manufacture
If conventional diode structure with P+ and N+ epitaxy on different oxide definitions is used, then the diode function is achieved, but the current path disappears when substrate is thinned
Solution Approach 1:
The patent merges the P+ and N+ epitaxial regions within the same oxide definition region, creating a lateral junction diode structure. This integration ensures that both epitaxial regions remain connected through the substrate without requiring separate oxide definitions, maintaining current path continuity even when the substrate is thinned for backside power delivery.
3Reliability
If BEOL processing is used for power delivery network, then the power supply is provided, but the capacitance and IR drop increase degrading chip performance
Solution Approach 1:
The patent moves the power delivery path from the front-side BEOL interconnects to the backside of the wafer. By implementing the lateral diode structure on the backside with current paths extending laterally through epitaxial layers, power can be delivered directly to active devices without sharing interconnect resources with signal lines, eliminating BEOL capacitance and IR drop issues.
Data Source
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AI summary
The present invention provides a semiconductor structure, wherein the semiconductor structure includes an oxide definition region, a plurality of metal gate structures and a plurality of S/D contacts. The oxide definition region is disposed over a semiconductor substrate and surrounded by insulating regions. The plurality of metal gate structures are disposed on an N-well or a P-well manufactured on the semiconductor substrate. The plurality of S/D contacts are disposed on the N-well or the P-well manufactured on the semiconductor substrate. In addition, the plurality of metal gate structures, the plurality of S/D contacts and the at least one dummy gate structure are within the oxide definition region.