Lateral Diode Channel Layout for Low-Capacitance ESD Protection
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Solution Overview
Problem
In stacked transistor technologies, traditional diodes formed by parasitic drain/source-body junctions are not realizable due to back-side isolation, leading to increased capacitance and lower failure current in area-constrained channel configurations, such as nanowire/ribbon/sheet channels.
Innovation Solution
Repurpose transistor channels as lateral diodes by configuring laterally neighboring source and drain regions with different polarity epitaxial growths to form an anode and cathode, utilizing techniques like skipping epitaxial regions, elongating gates, and using sub-fin conduction paths to reduce parasitics and enhance current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional parasitic drain/source-body junction diodes are used in stacked transistor technologies, then diode protection is provided, but the capacitance increases and failure current decreases in area-constrained channel configurations
Solution Approach 1:
The patent transitions from traditional vertical parasitic junction diodes to lateral diodes formed in the channel region, utilizing the horizontal dimension of the channel for diode formation. This dimensional change allows the diode to be integrated within the channel area without adding vertical complexity, thereby reducing parasitic capacitance while maintaining ESD protection functionality in stacked transistor architectures
Solution Approach 2:
The channel region is designed to serve dual purposes: as the conduction path for transistor operation and as the diode structure for ESD protection. By configuring laterally neighboring source and drain regions with different polarity epitaxial growths, the channel simultaneously functions as both the transistor channel and the diode junction, eliminating the need for separate diode structures and reducing overall capacitance
2Productivity
If area-constrained channel configurations (nanowire/ribbon/sheet channels) are used to increase transistor density, then transistor density improves, but diode failure current decreases
Solution Approach 1:
The patent merges the transistor channel and diode structure into a single integrated entity. The channel region serves as both the transistor conduction path and the diode junction, with source and drain regions providing both transistor terminals and diode contacts. This merging allows the diode to leverage the full channel area for current carrying capability while maintaining the area constraints necessary for high transistor density
Solution Approach 2:
The lateral diode configuration utilizes the horizontal extent of the channel region rather than relying on vertical junction depth. By forming the diode junction laterally across the channel width and length, the structure maximizes the use of available channel area for both transistor operation and ESD protection, enabling adequate failure current in area-constrained configurations
3Object-affected harmful factors
If lateral diodes are formed by repurposing transistor channels, then parasitic capacitance is reduced and current carrying capability increases, but additional epitaxial processing steps are required
Solution Approach 1:
The patent applies different epitaxial growth conditions to specific local regions of the channel structure. Laterally neighboring source and drain regions receive different polarity epitaxial growths (n-type and p-type), creating localized doping variations that form the diode junction. This local differentiation is achieved through selective masking and targeted epitaxial processing, integrating the diode formation into the existing transistor manufacturing flow without requiring comprehensive process changes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for higher current carrying capability, reduced parasitic capacitance, and improved ESD protection in stacked transistor technologies, particularly in gate-all-around devices, without requiring special interconnect processes or deviations from standard gate processing.
Implementation Method 1
configuring laterally neighboring source and drain regions with different polarity epitaxial growths to form an anode and cathode
Data Source
AI summary
Integrated circuits including lateral diodes. In an example, diodes are formed with laterally neighboring source and drain regions (diffusion regions) configured with different polarity epitaxial growths (e.g., p-type and n-type), to provide an anode and cathode of the diode. In some such cases, dopants may be used in the channel region to create or otherwise enhance a PN or PIN junction between the diffusion regions and the semiconductor material of a channel region. The channel region can be, for instance, one or more nanoribbons or other such semiconductor bodies that extend between the oppositely-doped diffusion regions. In some cases, nanoribbons making up the channel region are left unreleased, thereby preserving greater volume through which diode current can flow. Other features include skipped epitaxial regions, elongated gate structures, using isolation structures in place of gate structures, and/or sub-fin conduction paths that are supplemental or alternative to a channel-based conduction path.