Lateral Passive Diode Layout Within Nanosheet FET Stacks
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Solution Overview
Problem
In semiconductor device fabrication, there is a challenge in co-integrating passive/diodes with nanosheet logic on the same substrate, especially when access to the backside semiconductor substrate is not possible, requiring tall N and P type junctions without implanted junctions.
Innovation Solution
A semiconductor structure is developed that includes a lateral passive diode co-integrated with nanosheet stacked FET technology. The structure features a passive/diode device region with a diode located between two nanosheet stacks, comprising doped semiconductor pillars and an intrinsic semiconductor pillar, with backside and frontside contact structures for electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If lateral passive diodes are co-integrated with nanosheet stacks on the same substrate, then device integration density and functionality are improved, but fabrication process complexity increases
Solution Approach 1:
The patent merges the fabrication processes for nanosheet transistors and lateral passive diodes into a unified flow. Both device types are formed using the same epitaxial growth steps, doping processes, and contact formation sequences, allowing co-integration on the same substrate without requiring separate fabrication lines or additional processing stages.
Solution Approach 2:
The fabrication process is designed to be universal, serving multiple functions: it creates both active nanosheet transistors and passive diodes using identical material deposition, doping, and patterning techniques. This multi-functional approach allows a single process suite to produce diverse device types with different electrical characteristics from the same substrate.
2Reliability
If tall N and P type junctions are formed without backside substrate access, then electrical functionality is achieved, but manufacturing difficulty increases
Solution Approach 1:
The patent transitions from vertical junction formation (requiring backside access) to lateral junction formation. By forming N and P type regions side-by-side in the same epitaxial layer rather than stacking them vertically, the process eliminates the need for backside substrate access while maintaining the electrical functionality of tall junctions through lateral separation and selective contact formation.
Solution Approach 2:
The substrate surface is segmented into distinct regions for forming N type junctions and P type junctions laterally adjacent to each other. This spatial segmentation allows independent optimization of each junction type's electrical characteristics while using the same fabrication processes, avoiding the complexity of through-substrate processing.
3Area of stationary object
If diodes are formed between nanosheet stacks, then footprint efficiency is improved, but device complexity increases
Solution Approach 1:
The lateral passive diodes are nested between adjacent nanosheet transistor stacks, utilizing the space between active devices. This nesting arrangement allows diodes to share the same substrate real estate as transistors without interfering with transistor operation, achieving high integration density by fitting passive components into the interstices of active device arrays.
Data Source
AI summary
A semiconductor structure is provided that includes a lateral passive diode co-integrated with nanosheet stacked FET technology. Notably, the semiconductor structure includes a passive/diode device region including a lateral passive diode that is located between two nanosheet stacks. In embodiments, a logic device region including a stacked nanosheet transistor is located adjacent to the passive/diode device region.