Lateral DMOS Shallow Trench Isolation for Area Reduction
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Solution Overview
Problem
Conventional lateral DMOS devices face challenges in reducing size while maintaining high voltage sustain performance and low on-resistance, which is crucial for mobile and handheld electronic devices.
Innovation Solution
The design incorporates a shallow trench isolation structure with a conductive field plate and specific dopant concentrations, allowing for reduced lateral size and on-resistance while maintaining high breakdown voltage, achieved through a semiconductor layer structure with a well region, source and drain regions, and a second gate region with a shallow trench isolation structure and conductive field plate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the lateral size of the DMOS is reduced, then the device area is decreased, but the high voltage sustain performance deteriorates
Solution Approach 1:
The patent introduces a vertical dimension by forming a shallow trench isolation structure that extends vertically into the well region. This vertical structure allows the device to maintain high voltage sustain capability through increased vertical separation while reducing lateral footprint, effectively trading lateral space for vertical space to resolve the contradiction between device area and high voltage performance.
Solution Approach 2:
The shallow trench isolation structure is nested within the well region, with the trench extending vertically into the doped well. This nested configuration allows the isolation structure to be integrated within the existing device geometry without requiring additional lateral space, enabling area reduction while maintaining voltage sustain performance through the vertical nesting approach.
2Area of stationary object
If the lateral size of the DMOS is reduced, then the device area is decreased, but the on-resistance increases
Solution Approach 1:
The patent applies local quality by creating a shallow trench isolation structure with specific doping characteristics localized in the well region. The trench is formed with particular depth and width parameters, and the isolation structure incorporates specific dopant concentrations that are optimized locally to reduce on-resistance in the critical current path while maintaining overall device compactness.
3Area of stationary object
If a shallow trench isolation structure is formed, then the lateral size is reduced, but the device complexity increases
Solution Approach 1:
The shallow trench isolation structure segments the well region by creating a vertical separation through the trench. This segmentation divides the device into distinct regions with different electrical characteristics, allowing independent optimization of various device parameters. The trench acts as a physical and electrical separator that enables compact lateral dimensions while managing the complexity through functional segmentation of the device structure.
Data Source
AI summary
A lateral DMOS having a well region, a source region, a drain region, a first gate region and a second gate region. The first gate region may be positioned atop a portion of the well region near the source region side. The second gate region may be formed in a portion of the well region near the drain region side. The second gate region includes a shallow trench isolation structure formed in a shallow trench opened from a top surface of the well region and extended vertically into the well region, and having a first sidewall contacting with the drain region or abut the drain region, and further having a second sidewall opposite to the first sidewall and laterally extended below the first gate region.