Lateral Doping Profiles in SOI Devices for RF Performance

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Solution Overview

Problem

In advanced CMOS technology, improving the doping profile, gate-oxide thickness, and contacts in the vertical direction is challenging, particularly for devices like variable capacitors and field-effect transistors, due to limited junction depth, which hinders performance in analog and high-voltage applications such as RF and automotive systems.

Innovation Solution

The semiconductor device structure incorporates laterally arranged semiconductor regions with different doping types or concentrations, and an insulative layer to form non-insulative regions, allowing for improved doping profile options with minimal additional process steps, enabling better performance in variable capacitors and MOSFETs on silicon-on-insulator wafers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If vertical doping profile improvement is pursued in advanced CMOS technology, then device performance in analog and high-voltage applications is improved, but manufacturing complexity and process difficulty increase due to limited junction depth

Engineering Contradiction:
Improvedevice performanceVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent transitions from vertical doping profiles to lateral doping profiles by arranging semiconductor regions with different doping types or concentrations in a lateral configuration. This dimensional change allows improved doping control and device performance without requiring deeper junctions or more complex vertical processing, thereby resolving the contradiction between reliability improvement and manufacturing complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If lateral semiconductor regions with different doping types are incorporated, then doping profile flexibility is improved, but device structure complexity increases

Engineering Contradiction:
Improvedoping profile flexibilityVSAvoiddevice structure complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by creating distinct semiconductor regions with different doping types or concentrations at specific lateral positions. Each region is optimized for its local function, providing doping profile flexibility and adaptability while maintaining a relatively simple overall device structure that does not require complex multi-layer vertical stacking.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances device performance by allowing more flexible doping profiles and reduced parasitic capacitance, improving the quality factor and tuning range of semiconductor devices with minimal cost and process complexity.

Implementation Method 1

reduced parasitic capacitance

Methodology Applied
Scientific EffectParasitic capacitance reduction: Capacitance

Data Source

PatentUS10424641B1Lateral devices in silicon-on-insulator (SOI) technology
Publication Date: 2019.09.24 QUALCOMM INC
  • US10424641B1 patent drawing
  • US10424641B1 patent drawing
  • US10424641B1 patent drawing

AI summary

Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a first semiconductor region; a first non-insulative region disposed adjacent to a first lateral side of the first semiconductor region; a second non-insulative region disposed adjacent to a second lateral side of the first semiconductor region, the second lateral side being opposite to the first lateral side; a second semiconductor region disposed adjacent to a third lateral side of the first semiconductor region, the second semiconductor region and the first semiconductor region having at least one of different doping types or different doping concentrations; an insulative layer adjacent to a top side of the first semiconductor region; and a third non-insulative region, the insulative layer being disposed between the third non-insulative region and the first semiconductor region.