Lateral DRAM Capacitor Layout to Prevent Collapse at Small Cell Sizes

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Solution Overview

Problem

As semiconductor fabrication technology advances, the reduced size of DRAM memory circuits poses challenges such as collapse or wobbling during manufacturing, necessitating improvements to address these manufacturing challenges.

Innovation Solution

The memory device design features capacitors that extend laterally over a semiconductor substrate, with capacitor dielectrics and top electrodes conformal to recesses and in contact with bottom electrodes, allowing for electrical connection in parallel and improved manufacturing processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If DRAM memory circuit size is reduced to a few nanometers, then storage density is improved, but structural stability deteriorates causing collapse or wobbling during manufacturing

Engineering Contradiction:
ImproveDRAM cell sizeVSAvoidstructural stability
Core Design Contradiction:
Area of moving objectVSStability of the object's composition

Solution Approach 1:

The patent transitions from vertical capacitor stacking to lateral extension of capacitors along the semiconductor substrate. The capacitors extend in the lateral direction rather than vertically, changing the dimensional orientation from vertical to horizontal. This lateral configuration maintains structural stability while achieving high storage density through extended lateral dimensions rather than vertical stacking.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The memory device is divided into multiple separate capacitor units that extend laterally along the substrate. Each capacitor is an independent structural unit with bottom electrode, capacitor dielectric, and top electrode. This segmentation allows each unit to maintain individual structural integrity while collectively achieving high storage density through parallel arrangement.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If capacitors are arranged in multiple levels, then storage capacity is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvestorage capacityVSAvoidmanufacturing complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent merges multiple capacitor units into a single lateral array structure that extends along the substrate. Instead of creating separate vertical stacks that would require complex alignment and fabrication, the capacitors are combined into a continuous lateral structure with shared bottom electrodes and systematically arranged top electrodes, simplifying the manufacturing process while maintaining high storage capacity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The lateral capacitor structure serves multiple functions simultaneously: it provides high storage capacity through extended lateral dimensions, maintains structural stability through planar configuration, and enables simplified manufacturing through uniform fabrication processes. The same structural approach can be applied across the entire substrate area, making the design universally applicable and manufacturable.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12238917B2Memory device having laterally extending capacitors of different lengths and levels
Publication Date: 2025.02.25 NAN YA TECH
  • US12238917B2 patent drawing
  • US12238917B2 patent drawing
  • US12238917B2 patent drawing

AI summary

The present application provides a memory device having laterally extending capacitors of different lengths and levels. The memory device includes a semiconductor substrate; a first insulating layer disposed over the semiconductor substrate; a first bottom electrode disposed over the first insulating layer; a first dielectric layer disposed over the first bottom electrode; a first recess extending through the first dielectric layer; a first capacitor dielectric conformal to the first recess and in contact with the first bottom electrode; and a first top electrode disposed within the first recess and surrounded by the first capacitor dielectric, wherein the first capacitor dielectric and the first top electrode extend laterally over the first bottom electrode and the semiconductor substrate.