Lateral Floating-Gate Layout to Prevent Dielectric Shorts
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Solution Overview
Problem
The existing manufacturing processes for semiconductor devices with stacked configurations face challenges such as dielectric material deterioration, leading to shorts between gates and terminals, and complexities in multi-layer photo alignment.
Innovation Solution
The proposed solution involves arranging the first and second control gates laterally instead of in a stacked configuration, with a floating gate and dielectric material in between. This configuration reduces the proximity of control gates to electrodes, thereby minimizing dielectric material deterioration. Additionally, the manufacturing process is optimized by reducing the number of polysilicon material depositions, photoresist applications, and etching steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If control gates are arranged in a stacked configuration close to electrodes, then device integration density is improved, but dielectric material deteriorates leading to shorts between gates and terminals
Solution Approach 1:
The patent transitions from a vertical stacked configuration to a lateral arrangement of control gates, changing the spatial dimension of gate placement. This dimensional change increases the distance between control gates and electrodes, reducing dielectric stress and preventing shorts while maintaining device integration.
Solution Approach 2:
The patent divides the gate structure into multiple control gates arranged laterally rather than stacking them vertically. This segmentation distributes the electrical control functions across separate lateral positions, reducing the proximity-induced dielectric deterioration that occurs in stacked configurations.
2Adaptability or versatility
If stacked gate configuration is used, then manufacturing process complexity increases with multiple depositions and photo alignment steps, but device functionality is achieved
Solution Approach 1:
The patent combines multiple gate formation operations into a single lateral arrangement process. Instead of requiring separate depositions and photo alignment steps for each stacked gate layer, the lateral configuration allows gates to be formed in one continuous process, reducing manufacturing complexity while maintaining multi-gate functionality.
Solution Approach 2:
The lateral gate arrangement uses a universal manufacturing process that can form multiple control gates simultaneously using the same deposition and etching steps. This multi-functional approach eliminates the need for repeated photo alignment operations required in stacked configurations, simplifying the overall manufacturing process.
Data Source
AI summary
In some implementations, one or more semiconductor processing tools may deposit a first dielectric layer on a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a floating gate on the first dielectric layer. The one or more semiconductor processing tools may deposit a second dielectric layer on the floating gate and on the substrate of the semiconductor device. The one or more semiconductor processing tools may deposit a first control gate on a first portion of the second dielectric layer. The one or more semiconductor processing tools may deposit a second control gate on a second portion of the second dielectric layer, wherein a third portion of the second dielectric layer is between the first control gate and the floating gate and between the second control gate and the floating gate.