Lateral GaN Packaging Structure for Isolation and Thermal Dissipation
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Solution Overview
Problem
Conventional packaging formats for lateral GaN power electronic devices suffer from vertical leakage current and incompatibility with JEDEC standard frames due to the silicon substrate's limitations in sustaining high voltage, leading to substrate leakage and abnormal dynamic behavior during high power and high voltage operations.
Innovation Solution
A packaging structure that includes a lateral semiconductor power device chip with a semi-conductive adhesive layer and a back-plate, where the back-plate has a metal portion and an electrically insulating, thermally conducting portion, which is either semi-insulating or ceramic, to prevent vertical leakage current and allow for standard JEDEC frame compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional packaging formats are used for lateral GaN devices, then the packaging is compatible with standard vertical device formats, but vertical leakage current occurs due to the silicon substrate's inability to sustain high voltage
Solution Approach 1:
The back-plate is segmented into multiple functional portions: a first portion electrically connected to the drain electrode, a second portion forming an adhesive area with the semiconductor chip, and a third portion electrically connected to the source electrode. This segmentation allows each portion to perform its specific function (electrical connection, mechanical bonding, and current path management) independently, preventing vertical leakage while maintaining packaging compatibility
Solution Approach 2:
The adhesive layer serves as an intermediary between the back-plate and the semiconductor chip, providing both mechanical bonding and electrical isolation. This intermediary structure enables the back-plate to mechanically support the device while preventing direct electrical contact that would cause vertical leakage current through the silicon substrate
2Strength
If the silicon substrate is used to sustain high voltage, then the device can operate at high voltage, but substrate leakage occurs when voltage exceeds 1,000 V
Solution Approach 1:
The electrical connection path is extracted from the silicon substrate by routing current through the metal back-plate structure instead. The back-plate's first portion connects to the drain, and the third portion connects to the source, creating an external current path that bypasses the silicon substrate and prevents high-voltage stress from causing substrate leakage
Solution Approach 2:
The back-plate utilizes composite material structure combining metal portions for electrical connection and adhesive areas for mechanical bonding. This composite structure provides both the electrical conductivity needed for high-voltage operation and the mechanical adhesion required for device reliability, eliminating the substrate leakage problem
3Ease of operation
If electrodes are arranged on the same side for lateral devices, then current flows laterally across the device, but conventional packaging formats cannot be used
Solution Approach 1:
The packaging structure extends into the vertical dimension by using a back-plate that contacts the lower surface of the chip, complementing the lateral electrode arrangement on the upper surface. This three-dimensional packaging approach accommodates lateral current flow on the chip surface while providing vertical mechanical support and electrical connections through the back-plate, achieving compatibility with standard packaging formats
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces or eliminates substrate vertical leakage current, enhances breakdown voltage, and improves dynamic behavior during high-speed switching, while allowing for the use of standard packaging formats, thereby improving the reliability and efficiency of GaN power devices.
Implementation Method 1
a semi-conductive adhesive layer disposed between the lower surface of the lateral semiconductor power device chip and the back-plate
Implementation Method 2
The back-plate includes at least a metal portion that is electrically connected to a second electrode of the at least two electrodes
Implementation Method 3
the electrically insulating and thermally conducting portion of the back-plate
Data Source
AI summary
Packaging structures for lateral high voltage gallium nitride (GaN) devices achieve electrical isolation while also maintaining thermal dissipation is provided. The electrical isolation reduces or eliminates vertical leakage current, improving high voltage performance with the semi-insulating layer for adhering the lateral semiconductor power device chip to the back-plate. The packages may use or be compatible standards such as JEDEC, which reduces packaging cost and facilitates implementation of the packaged devices in conventional circuit design approaches.