CMOS-Compatible Lateral IGBT on Bulk Silicon

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Solution Overview

Problem

Current power semiconductor devices integrating LDMOS with lateral IGBTs are not compatible with CMOS processes and typically use expensive SOI substrates, limiting their integration and cost-effectiveness.

Innovation Solution

A power semiconductor device design that incorporates a P-type silicon substrate with deep N wells, P-grade regions, shallow trench isolation regions, and gate electrodes, forming a CMOS-compatible lateral IGBT structure using a bulk silicon substrate, allowing for efficient integration and reduced costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If lateral IGBT is formed using SOI substrate, then integration capability is improved, but manufacturing cost increases due to extra masks and substrate expense

Engineering Contradiction:

Improveintegration capabilityVSAvoidmanufacturing cost

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent replaces expensive SOI substrates with standard bulk silicon substrates, using a disposable-like approach where the substrate is a common, inexpensive material that is processed and discarded after single use in the device fabrication, thereby reducing substrate and processing costs while achieving the desired device functionality

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent changes the substrate parameter from SOI (silicon-on-insulator) to bulk silicon, fundamentally altering the substrate structure to eliminate the need for expensive SOI processing while maintaining the lateral IGBT functionality through modified device architecture including deep N-well and specific doping profiles

Inventive Principle:

Principle #35Parameter changes

2Loss of energy

If LDMOS and lateral IGBT are integrated, then power switching efficiency is improved, but device complexity increases

Engineering Contradiction:

Improvepower switching efficiencyVSAvoiddevice complexity

Core Design Contradiction:

Loss of energyVSDevice complexity

Solution Approach 1:

The patent merges LDMOS and lateral IGBT devices into a single integrated structure on the same bulk silicon substrate, sharing common regions such as the deep N-well and utilizing overlapping fabrication processes, thereby achieving power switching efficiency benefits while managing device complexity through structural integration rather than separate discrete devices

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent creates a universal device structure where the deep N-well and associated regions serve multiple functions for both LDMOS and lateral IGBT operations, allowing a single fabricated structure to perform multiple power switching functions, reducing overall system complexity despite the advanced functionality achieved

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20100155895A1Power semiconductor device

Publication Date: 2010.06.24 UNITED MICROELECTRONICS CORP

AI summary

A power semiconductor device includes a P type silicon substrate; a deep N well in the P type silicon substrate; a P grade region in the deep N well; a P+ drain region in the P grade region; a first STI region in the P grade region; a second STI region in the P grade region, wherein the first and second STI region isolate the P+ drain region; a third STI region in the deep N well; a gate electrode overlying an area between the second and third STI regions and covering a portion of the second STI region; a gate dielectric layer between the gate electrode and the P type silicon substrate; a P well formed at one side of the third STI region; and a P+ source region in the P well.