Lateral Interconnect Via for Buried Rail FinFET Connection
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Solution Overview
Problem
Current methods for connecting fin-based active devices to buried interconnect rails in semiconductor processing result in deep and narrow vias, increasing resistivity and parasitic capacitance due to lithography constraints and the use of local interconnects.
Innovation Solution
The method involves creating an interconnect via between a buried rail and a contact area on a semiconductor fin without using a metallization level above the active devices, with the via extending partially above the rail and covered by a dielectric layer, allowing direct contact between the via and the contact area's lateral portion, thereby eliminating the need for local interconnects in the M0 metallization level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interconnect via is made deep and narrow to reach buried rail, then connection is established, but resistivity increases
Solution Approach 1:
The patent transitions from a vertical via connection to a lateral connection by forming the interconnect via to contact the lateral portion of the contact area. This dimensional change allows the via to have a larger cross-sectional area while still reaching the buried rail, thereby reducing resistivity while maintaining connection reliability.
2Object-affected harmful factors
If via width is increased to reduce resistivity, then resistivity decreases, but lithography constraints are violated
Solution Approach 1:
The patent resolves the lithography constraint by changing the via orientation from vertical to lateral. The lateral via can extend further in the horizontal plane without violating lithography resolution limits, allowing for a larger effective cross-sectional area and reduced resistivity while remaining within manufacturing capabilities.
Solution Approach 2:
The patent changes the geometric parameters of the interconnect via by extending it laterally rather than vertically. This parameter change allows the via to achieve a larger cross-sectional area for current conduction while maintaining dimensions that are compatible with lithography process constraints.
3Reliability
If local interconnect is used to connect transistor to buried rail, then connection is established, but parasitic capacitance increases
Solution Approach 1:
The patent extracts and eliminates the local interconnect layer from the connection path between the transistor contact area and the buried rail. By forming a direct lateral via connection, the patent removes the intermediate local interconnect structure that would otherwise contribute parasitic capacitance to the gate.
Solution Approach 2:
The patent merges the contact area and the interconnect via into a single integrated structure where the via directly contacts the lateral portion of the contact area. This merging eliminates the separate local interconnect layer and reduces the overall parasitic capacitance by minimizing the number of interfaces and overlapping conductive structures.
Data Source
AI summary
An integrated circuit chip having fin-based active devices in the front end of line, and an electrical connection between a buried interconnect rail and a contact area on a semiconductor fin, such as an epitaxially grown source or drain contact area of a transistor, is disclosed. In one aspect, the electrical connection is realized without the intervention of a metallization level formed above the active devices in the IC. Instead, an interconnect via is produced between the buried interconnect rail and a lateral portion of the contact area, wherein the lateral portion is directly contacted by a sidewall of the interconnect via. Methods for producing the interconnect via are also disclosed.