Lateral MOS Gate Dielectric Extension for Higher Breakdown Voltage
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Solution Overview
Problem
Lateral double-diffused MOS (LDMOS) devices face breakdown issues at the gate-to-drain side due to high peak electric fields, leading to reduced breakdown voltage without increasing device footprint, which affects device density and wafer cost.
Innovation Solution
Incorporating an extension of the dielectric layer partway underneath the drain-facing side of the gate through a two-step etch process, including anisotropic and isotropic etching to form a cavity, followed by dielectric deposition, reduces the peak electric field without altering the device's physical dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate-to-drain length is increased to reduce peak electric field, then breakdown voltage is improved, but device footprint increases
Solution Approach 1:
The patent applies local quality by extending the dielectric layer only in the specific region underneath the drain-facing side of the gate, rather than uniformly across the entire device. This localized modification reduces peak electric field at the critical gate-to-drain interface, improving breakdown voltage without increasing the overall device footprint. The dielectric extension is precisely positioned where the electric field stress is highest, providing targeted field management.
Solution Approach 2:
The patent resolves the contradiction by transitioning from a two-dimensional solution (increasing gate-to-drain length in the lateral plane) to a three-dimensional solution (extending the dielectric layer vertically underneath the gate). This dimensional change allows field reduction without lateral expansion, as the dielectric extension projects downward into the substrate rather than outward in the device plane.
2Manufacturing precision
If a two-step etch process is used to form dielectric extension, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by performing the two-step etch process to create the cavity and positioning structure before depositing the dielectric layer. The first etch step prepares the cavity with precise dimensions, and the second etch step creates the undercut structure that will hold the dielectric extension. This preliminary structuring ensures that when the dielectric is deposited, it automatically forms the extension in the correct position with the required precision, without needing additional alignment steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances breakdown voltage by approximately 3.5% while maintaining device density and fabrication yield, offering a robust and efficient method for improving LDMOS performance.
Implementation Method 1
performing photolithographically patterned etching of the gate layer to form a first side of a gate facing the source of the lateral MOS device
Implementation Method 2
performing photolithographically patterned etching of the gate layer to form a second side of the gate facing the drain of the lateral MOS device and to etch a cavity extending partway underneath the second side of the gate
Implementation Method 3
forming a dielectric layer at least on the first and second sides of the gate and filling the cavity extending partway underneath the second side of the gate
Data Source
AI summary
In fabricating a lateral metal oxide semiconductor (MOS) device, source and drain regions are formed in a base semiconductor. A gate oxide layer is disposed on the base semiconductor, and a gate layer on the gate oxide layer. Photolithographically patterned etching of the gate layer forms a first side of the gate facing the source. Photolithographically patterned etching of the gate layer forms a second side of the gate facing the drain of the lateral MOS device, and also etches a cavity extending partway underneath the second side of the gate. A dielectric layer is formed at least on the first and second sides of the gate and filling the cavity extending partway underneath the second side of the gate.