Lateral N-P Junction Isolation for TID Hardened MOS Transistors

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Solution Overview

Problem

NMOS high-voltage transistors are vulnerable to ionizing radiation, leading to transistor off-state leakage due to positive charge deposition in insulating materials, causing parasitic drain-to-source leakages and limiting their usable lifetime, with existing solutions like annular gate geometries and additional p-type implants either being unsatisfactory or degrading junction breakdown.

Innovation Solution

Creating a lateral n-p junction to isolate the device channel from the sidewall of the STI isolation structure on both source and drain regions, with additional p-type implants to increase Total Ionizing Dose (TID) immunity, and replacing shallow-trench isolation with an engineered junction to reduce impedance and prevent single-event transients and latchups.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If additional p-type implants are added to increase parasitic Vt and improve TID immunity, then TID immunity is improved, but junction breakdown performance is degraded

Engineering Contradiction:

ImproveTID immunityVSAvoidjunction breakdown performance

Core Design Contradiction:

ReliabilityVSStrength

Solution Approach 1:

The patent applies local quality by creating a lateral n-p junction specifically at the drain region to isolate the channel from STI sidewalls, rather than uniformly doping the entire device. This localized approach provides TID immunity where needed (at the vulnerable drain-STI interface) without degrading the overall junction breakdown performance of the transistor.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The lateral n-p junction acts as an intermediary structure between the drain and the STI isolation structure. This intermediate layer prevents direct interaction between the drain electric field and the STI sidewalls, thereby blocking the formation of parasitic transistors while maintaining the electrical integrity of the main junction.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If shallow-trench isolation is used to isolate transistor regions, then isolation effectiveness is improved, but single-event transients and latchups occur due to positive charge accumulation

Engineering Contradiction:

Improveisolation effectivenessVSAvoidsingle-event transients and latchups

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent converts the harmful effect of positive charge accumulation in STI into a beneficial isolation mechanism. By allowing the STI to retain its charge accumulation property while introducing a lateral n-p junction, the positive charge actually enhances the isolation effect by further increasing the potential barrier at the drain-STI interface, preventing carrier injection and parasitic transistor formation.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

3Object-generated harmful factors

If annular gate geometries are used to prevent parasitic transistors, then parasitic leakage is reduced, but device complexity and manufacturing difficulty increase

Engineering Contradiction:

Improveparasitic leakageVSAvoiddevice complexity

Core Design Contradiction:

Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

Instead of using an annular gate geometry that completely encircles the drain, the patent inverts the approach by using a lateral n-p junction that extends from the drain toward the STI sidewall. This inverted isolation strategy achieves the same goal of preventing parasitic transistor formation but with a simpler, more manufacturable structure that is compatible with standard planar fabrication processes.

Inventive Principle:

Principle #13The other way round (Inversion)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively isolates the transistor channel from radiation-induced leakage, enhances TID immunity, and maintains junction breakdown performance, allowing for scalable transistor design and reduced parasitic leakage, while being compatible with standard semiconductor fabrication processes.

Implementation Method 1

lateral n-p junction is created in the transistor to isolate the device channel from the sidewall of the STI isolation structure on both the source and drain regions

Methodology Applied

Scientific EffectParasitic transistor threshold voltage effect:

Implementation Method 2

additional p-type implants to increase the parasitic Vt and improve TID immunity

Methodology Applied

Scientific EffectDoping effect:

Implementation Method 3

replacing shallow-trench isolation with an engineered junction to reduce impedance and prevent single-event transients and latchups

Methodology Applied

Scientific EffectImpedance reduction:

Data Source

PatentUS9093517B2TID hardened and single event transient single event latchup resistant MOS transistors and fabrication process

Publication Date: 2015.07.28 MICROSEMI SOC CORP

AI summary

A radiation-hardened transistor is formed in a p-type body. An active region is disposed within the p-type body and has a perimeter defined by a shallow-trench isolation region filled with a dielectric material. Spaced-apart source and drain regions are disposed in the active region, forming a channel therebetween. A polysilicon gate is disposed above, aligned with, and insulated from the channel region. A p-type isolation ring is disposed in the p-type body separating outer edges of at least one of the source and drain regions from the perimeter of the active region. A body contact is disposed in the p-type isolation ring.