Lateral Overlapping Near-Conductive Layers for IC Signal Coupling
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Solution Overview
Problem
Current IC packaging technologies limit signal bandwidth between integrated circuit packages due to the use of plated through hole vias, which introduce parasitic inductance and capacitance, impairing data rate and frequency response.
Innovation Solution
The solution involves a package system where near-conductive layers, closer to the IC chip, are used to electrically couple contact structures between two IC packages without relying on plated through hole vias, allowing direct signal transmission between IC chips through laser vias, thereby reducing parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If plated through hole vias are used to electrically couple IC packages, then electrical connection between packages is achieved, but parasitic inductance and capacitance increase, degrading signal bandwidth and data rate
Solution Approach 1:
The patent extracts and eliminates the plated through hole vias from the electrical connection path between IC packages. By removing this intermediate connection method and directly coupling the near-conductive layers of adjacent packages, the source of parasitic inductance and capacitance is eliminated, thereby improving signal bandwidth while maintaining electrical connection reliability
Solution Approach 2:
The near-conductive layers serve as an intermediary structure that enables direct electrical coupling between IC packages without requiring plated through hole vias. These layers are positioned to face each other across the package interface, creating a direct signal path that minimizes parasitic effects while maintaining reliable electrical connection
2Speed
If near-conductive layers are used for direct electrical coupling, then parasitic effects are minimized and signal bandwidth is enhanced, but manufacturing complexity increases due to precise layer alignment requirements
Solution Approach 1:
The patent merges the electrical coupling function into the near-conductive layers themselves, eliminating the need for separate plated through hole via structures. By combining the signal transmission path with the package substrate structure, the design achieves high-speed signal transmission while the overlapping configuration provides inherent alignment tolerance that reduces manufacturing complexity
Solution Approach 2:
The patent transitions from vertical through-hole connections to lateral overlapping connections between near-conductive layers. This dimensional change allows signal transmission to occur through the overlapping region of adjacent packages, reducing the signal path length and parasitic effects while enabling parallel processing capabilities that improve overall system performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances signal transmission efficiency by minimizing parasitic effects, enabling higher data rates and improved frequency response without the need for plated through hole vias, thus overcoming the bandwidth limitations of existing technologies.
Implementation Method 1
plated through hole vias, which introduce parasitic inductance and capacitance, impairing data rate and frequency response
Data Source
AI summary
Aspects of the disclosure provide a package system that includes a first integrated circuit (IC) package and a second IC package. The first IC package includes a first IC chip mounted on a first substrate-chip surface of a first package substrate. The first package substrate includes first near-conductive layers that are closer to the first substrate-chip surface than first far-conductive layers. The second IC package includes a second IC chip mounted on a second substrate-chip surface of a second package substrate. The second package substrate includes second near-conductive layers that are closer to the second substrate-chip surface than second far-conductive layers. A first contact structure on the first substrate-chip surface and a second contact structure on the second substrate-chip surface electrically couple the first IC chip with the second IC chip through electrical connections in the first and second near-conductive layers.