Lateral Power Semiconductor Double-Gate Structure for Lower Switching Loss
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Solution Overview
Problem
Traditional power semiconductor devices face high switching loss and specific on resistance due to large current handling, which affects performance and life, and issues like hot-carrier injection and advanced breakdown from excessive electric field modulation.
Innovation Solution
A lateral power semiconductor device with a double gate structure, where the control gate is separately connected to different potentials, and the dielectric layer thickness is adjusted under the salicide block to reduce switching loss and specific on resistance, while maintaining breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a traditional LDMOS device is used with metal field plate connected to source electrode, then the device structure is simple, but the switching loss is large which affects performance and life
Solution Approach 1:
The gate structure is segmented into two independent gates: control gate and main gate. The control gate can be independently biased to assist depletion of the drift area, reducing switching loss. The main gate controls the channel current. This segmentation allows independent optimization of switching and conduction characteristics without increasing overall device complexity.
Solution Approach 2:
The control gate voltage is dynamically adjusted during switching operations. During turn-off, the control gate is biased negatively to enhance depletion and reduce tail current. During turn-on, the control gate voltage is raised to enable full conduction. This dynamic voltage adjustment optimizes switching performance while maintaining simple device structure.
2Reliability
If the control gate is used to assist drift area in depletion with negative potential, then the breakdown voltage can be maintained at higher drift area concentration, but hot-carrier effect and advanced breakdown may occur due to excessively strong electric field modulation
Solution Approach 1:
The dielectric layer thickness is made non-uniform: thicker under the control gate near the drain area and thinner under the main gate. This local variation in dielectric thickness modulates the electric field strength locally - stronger field under main gate for channel control, weaker field under control gate near drain to avoid hot-carrier injection and advance breakdown. This allows the control gate to assist depletion effectively while maintaining reliability.
Solution Approach 2:
The dielectric layer with varying thickness acts as an intermediary between the control gate and the drift area. It mediates the electric field modulation effect, allowing the control gate to exert sufficient influence for depletion assistance while preventing excessively strong fields that would cause hot-carrier effects. The dielectric layer buffers and distributes the electric field appropriately.
3Device complexity
If polysilicon with PN junction is used on the control gate, then the gate-drain coupling charge number and equivalent capacitance CGD are reduced, but the device complexity increases
Solution Approach 1:
The control gate material is changed from conventional metal or simple polysilicon to polysilicon with embedded PN junction. This parameter change in material composition and structure creates a junction that reduces the gate-drain capacitance by forming a depletion region that acts as an electrical barrier. The PN junction structure modifies the electric field distribution, reducing coupling charge and equivalent capacitance CGD, thereby reducing switching loss and improving device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves reduced switching loss, increased on current, and improved breakdown voltage with optimized electric field distribution, reducing hot-carrier injection effects and specific on resistance.
Implementation Method 1
a negative potential is given to the control gate to make the control gate assist a drift area in depletion... the thickness of an insulating dielectric layer under SAB is adjusted to make the dielectric layer close to a drain area thicker, so that the advanced breakdown problem of the device can be effectively relieved
Implementation Method 2
On the control gate, polysilicon with a PN junction is used, thereby reducing the gate-drain coupling charge number and the equivalent capacitance CGD
Implementation Method 3
the source electrode 9 is in ohmic contact with the first doping type source area 7, and the source electrode 9 is in ohmic contact with the second doping type second body area 6... the drain electrode 12 is in ohmic contact with the first doping type drain area 8
Data Source
AI summary
A lateral power semiconductor device is provided and includes a second doping type substrate, a first doping type buried layer, a second doping type epitaxial layer, a first doping type drift area, a second doping type first body area, a first doping type drain area, a first doping type source area, a second doping type second body area, a dielectric layer, a control gate, a body electrode, second doping type polysilicon and first doping type polysilicon. The control gate is led out and connected to different potentials; when the device is in an off state, the control gate is connected to a low potential to assist the drift area in depletion; and when the device is in an on state, the control gate is connected to a high potential, and more carriers are induced on a silicon surface below the control gate.