Lateral Power Semiconductor Interconnect Layout for Low On-Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional lateral power field effect transistors (FETs) suffer from increased parasitic resistance due to long, thin metal interconnects, which also elevate the on-resistance of the device, particularly as the die size increases and more transistor cells are connected in parallel.
Innovation Solution
A novel metal interconnect layout with multiple current pathways is introduced, comprising three metal layers with source and drain metal bars in specific orientations and a nonconductive layer ensuring solder bumps connect only to source or drain metal bars, reducing parasitic resistance and on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If long, thin metal interconnects are used to connect transistor cells, then the device can accommodate larger die size and more parallel transistor cells, but parasitic resistance and on-resistance increase
Solution Approach 1:
The patent transitions from planar (2D) metal interconnects to three-dimensional (3D) vertically-aligned conductive pillars. This dimensional change allows current to flow through multiple parallel vertical pathways, dramatically reducing parasitic resistance while accommodating larger die sizes with more parallel transistor cells.
Solution Approach 2:
The interconnect structure is segmented into multiple discrete conductive pillars distributed across the die. Each pillar provides an independent current pathway, and the collective array of pillars reduces overall parasitic resistance. The segmentation also allows optimization of individual pillar dimensions rather than relying on long continuous interconnects.
2Power
If more transistor cells are connected in parallel to withstand greater power, then power handling capability increases, but parasitic resistance and on-resistance increase due to longer interconnects
Solution Approach 1:
By implementing vertical conductive pillars, the patent creates multiple parallel current pathways that scale with the number of transistor cells. This allows power handling capability to increase while on-resistance remains low, as each additional transistor cell contributes additional vertical pillar pathways rather than extending horizontal interconnect length.
Solution Approach 2:
The patent merges the source and drain metal layers into vertically-aligned conductive pillars that directly connect to the transistor cells. This consolidation eliminates the need for separate, long horizontal interconnects, reducing parasitic resistance while maintaining the ability to handle greater power through parallel cell configurations.
3Device complexity
If conventional metal interconnects are used, then device structure is simple, but parasitic resistance increases reducing device performance
Solution Approach 1:
The conductive pillars are formed using composite material structures, combining different materials (e.g., semiconductor material for the pillar core with metal contacts) to achieve low resistance while maintaining structural integrity. This composite approach reduces parasitic resistance compared to conventional single-material interconnects while adding manageable complexity.
Solution Approach 2:
The patent replaces the conventional mechanical/planar metal interconnect system with a vertically-aligned conductive pillar system formed through semiconductor processing techniques. This substitution fundamentally changes the interconnect architecture, reducing parasitic resistance through the vertical current pathway while the complexity is managed through standard semiconductor fabrication processes.
Data Source
Figure 1A~1B
Figure 1C
Figure 2A~2B
AI summary
A lateral power semiconductor device with a metal interconnect layout for low on-resistance. The metal interconnect layout includes first, second, and third metal layers, each of which include source bars and drain bars. Source bars in the first, second, and third metal layers are electrically connected. Drain bars in the first, second, and third metal layers are electrically connected. In one embodiment, the first and second metal layers are parallel, and the third metal layer is perpendicular to the first and second metal layers. In another embodiment, the first and third metal layer are parallel, and the second metal layer is perpendicular to the first and third metal layers. A nonconductive layer ensures solder bumps electrically connect to only source bars or only drain bars. As a result, a plurality of available pathways exists and enables current to take any of the plurality of available pathways.