Lateral Power MOS Shielding via Universal Dielectric
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Solution Overview
Problem
Existing processes for manufacturing shielded power MOS lateral transistors in VLSI CMOS technology are complex, expensive, and introduce electrical variations, as they are not compatible with standard VLSI CMOS processes, and previous solutions either reduce device performance or are inefficient in reducing feedback capacitance and hot carriers.
Innovation Solution
A process involving the formation of a protection dielectric layer on the drift region, followed by a premetal dielectric layer with simultaneous openings aligned with source and drain regions to expose the protection dielectric layer, allowing for the creation of an electric shield without additional complex or expensive steps, optimizing electrical parameters like feedback capacitance and on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a shielding electrode is added to reduce feedback gate-drain capacitance, then the feedback capacitance and hot carriers phenomenon are reduced, but the manufacturing process complexity and cost increase due to additional dielectric layers and openings
Solution Approach 1:
The premetal dielectric layer is designed to serve dual purposes: as the standard premetal dielectric for VLSI CMOS devices and as the shielding dielectric for power MOS lateral transistors. This eliminates the need for a separate shielding dielectric layer, reducing manufacturing complexity while maintaining the feedback capacitance reduction benefit
Solution Approach 2:
The formation of openings for source and drain contacts is merged with the formation of the opening for the shielding electrode. All three openings are created simultaneously in the same premetal dielectric layer through a single photolithography and etching sequence, eliminating additional manufacturing steps
2Reliability
If a shielding electrode is added to reduce feedback gate-drain capacitance, then the hot carriers phenomenon is reduced, but the manufacturing cost increases due to additional process steps
Solution Approach 1:
The premetal dielectric layer performs both its conventional function and the additional function of shielding, eliminating the need for extra dielectric deposition processes and associated costs
Solution Approach 2:
The shielding electrode formation is combined with the source and drain contact formation in a single process sequence, eliminating additional photolithography, etching, and metallization steps that would increase manufacturing cost
3Reliability
If additional dielectric layers and openings are added for shielding, then feedback capacitance is reduced, but electrical variations are introduced that affect device performance
Solution Approach 1:
Using the existing premetal dielectric layer avoids the introduction of additional dielectric materials and interfaces that could cause electrical variations, maintaining process consistency across VLSI CMOS and power MOS devices
Solution Approach 2:
The simultaneous formation of all openings in a single process step ensures consistent dimensional control and reduces alignment errors, minimizing electrical variations in the final device characteristics
Data Source
AI summary
A process manufactures power MOS lateral transistors together with CMOS devices on a semiconductor substrate. The process forms a lateral MOS transistor having a gate electrode on the semiconductor region, a source comprising a first highly doped portion aligned with the gate electrode and a drain comprising a lightly doped portion aligned with the gate electrode and a second highly doped portion included in the lightly doped portion. The process forms on the lightly doped portion, a protective layer of a first material; forms on the lateral MOS transistor, a dielectric layer of a second material selectively etchable with respect to the first material; forms, in the dielectric layer first, second, and third openings; and fills the openings with a conductive layer that forms drain and source contacts electrically connected to the first and second highly doped portions, and one electrical shield substantially aligned with the protective layer.