Lateral Power MOSFET Isolation Layer Minority Carrier Confinement

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Solution Overview

Problem

Power semiconductor devices, such as power MOSFETs, experience power loss and reduced efficiency due to the body diode's slow reverse recovery time, which is exacerbated by minority carrier storage in the substrate, leading to increased total charge reverse recovery charge and characteristic time.

Innovation Solution

The implementation of a lateral power semiconductor device structure with an isolation layer and well regions formed in the substrate to reduce minority carrier storage, including the use of a P-type epitaxial layer or silicon-on-insulator substrate to confine and neutralize excess minority carriers near the PN junction, thereby reducing recovery time and charge.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If an external Schottky diode is placed in parallel with the semiconductor device, then reverse recovery losses are minimized, but circuit costs increase and additional board space is required

Engineering Contradiction:
Improvereverse recovery lossesVSAvoidcircuit costs and board space
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent merges the Schottky diode functionality into the power MOSFET structure by forming a Schottky contact directly on the substrate. This integration eliminates the need for an external Schottky diode, reducing circuit complexity and board space while maintaining the low reverse recovery loss benefit

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The substrate serves as an intermediary element that enables both the MOSFET operation and Schottky diode functionality. By forming a Schottky contact on the substrate, the substrate acts as a mediator that provides the fast recovery characteristics without requiring a separate external component

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If the body diode is used for current flow, then the device structure is simple, but reverse recovery time is slow and power loss increases

Engineering Contradiction:
Improvedevice structureVSAvoidpower loss
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

The patent applies local quality by creating a Schottky contact at a specific location on the substrate, giving that local region fast recovery characteristics. The rest of the device maintains its standard MOSFET structure, so the overall device complexity remains simple while the local Schottky region provides the energy loss reduction

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly reduces the reverse recovery time and total charge reverse recovery charge by confining minority carriers to a thin surface region, enhancing the power conversion efficiency of semiconductor devices without the need for external Schottky diodes.

Implementation Method 1

an isolation layer formed over the substrate for reducing minority carrier storage in the substrate

Methodology Applied
Scientific EffectMinority carrier storage reduction:

Data Source

PatentUS7842568B2Lateral power semiconductor device for high frequency power conversion system, has isolation layer formed over substrate for reducing minority carrier storage in substrate
Publication Date: 2010.11.30 GREAT WALL SEMICONDUCTOR CORP
  • US7842568B2 patent drawing
  • US7842568B2 patent drawing
  • US7842568B2 patent drawing

AI summary

A lateral power semiconductor device has a substrate and an isolation layer formed over the substrate for reducing minority carrier storage in the substrate. A well region is formed over the isolation layer. A source region, drain region, and channel region are formed in the well. A first region is formed on a surface of the lateral power semiconductor device adjacent to the source region. The lateral power semiconductor device has a body diode between the first region and drain region. The isolation layer confines the minority carrier charge from the body diode to a depth of less than 20 μm from the surface of the lateral power semiconductor device. In one embodiment, the isolation layer is a buried oxide layer and the substrate is an n-type or p-type handle wafer. Alternatively, the isolation layer is an epitaxial layer and the substrate is made with N+ or P+ semiconductor material.