Lateral SiC Semiconductor Device for High Breakdown Voltage
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Solution Overview
Problem
Power semiconductor devices, particularly those made from gallium nitride (GaN) and silicon carbide (SiC), face challenges in achieving reliable avalanche breakdown voltage and efficient current handling due to their material limitations and configurations, with GaN lacking a PN junction and SiC being suited only for vertical devices with high resistance and parasitic capacitance.
Innovation Solution
A lateral semiconductor configuration is developed using n-doped, p−-doped, and p+-doped layers with specific charges determined by dopant levels and physical dimensions, allowing SiC to be used in a lateral configuration, enabling robust performance with high breakdown voltage and current capacity, similar to GaN devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If SiC is used in vertical power devices, then device ruggedness and high power capability are improved, but substrate resistance increases and parasitic capacitance increases
Solution Approach 1:
The patent transitions from vertical current flow to lateral current flow in the semiconductor device. By arranging the n-doped layer, p−-doped layer, and p+-doped buffer layer in a lateral configuration rather than vertical stacking, the device achieves low parasitic capacitance while maintaining high power capability. The current flows horizontally through the layered structure, eliminating the vertical resistance and capacitance issues inherent in conventional SiC devices.
Solution Approach 2:
The patent modifies the doping parameters and layer thicknesses to optimize device performance. Specifically, the n-doped layer has a first dopant level and thickness, the p−-doped layer has a second dopant level and thickness, and the p+-doped buffer layer has a third dopant level and thickness. By carefully controlling these parameters, the device achieves high breakdown voltage while maintaining low on-resistance and low parasitic capacitance, resolving the contradiction between ruggedness and energy loss.
2Speed
If GaN material is used for lateral semiconductors, then fast switching and good figure of merit are improved, but avalanche breakdown voltage capability is lacking
Solution Approach 1:
The patent employs a composite layered structure combining n-doped SiC, p−-doped SiC, and p+-doped SiC buffer layer. This composite material approach leverages the advantages of SiC (high breakdown voltage capability) while configuring it in a lateral structure that enables fast switching. The combination of specific doping levels and layer thicknesses in this composite structure achieves both high switching speed and high avalanche breakdown voltage capability.
3Power
If vertical configuration is used for SiC devices, then high power capability is achieved, but current travels vertically incurring resistance
Solution Approach 1:
The patent fundamentally changes the current flow direction from vertical to lateral. The n-doped layer, p−-doped layer, and p+-doped buffer layer are arranged such that current flows horizontally through the device structure. This dimensional change eliminates the vertical substrate resistance path, reducing energy loss while maintaining high power capability through optimized layer doping and thickness parameters.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables SiC to be used in lateral semiconductor devices with improved figure of merit parameters, overcoming the limitations of substrate resistance and achieving high breakdown voltage and current handling capabilities, rivaling GaN devices.
Implementation Method 1
an n-doped layer having a first applied charge and a p−-doped layer having a second applied charge. The respective charges at each layer may be determined based on a dopant level and a physical dimension of the layer
Data Source
AI summary
A method and apparatus include an n-doped layer having a first applied charge, and a p−-doped layer having a second applied charge. The p−-doped layer may be positioned below the n-doped layer. A p+-doped buffer layer may have a third applied charge and be positioned below the p−-doped layer. The respective charges at each layer may be determined based on a dopant level and a physical dimension of the layer. In one example, the n-doped layer, the p−-doped layer, and the p+-doped buffer layer comprise a lateral semiconductor manufactured from silicon carbide (SiC).