Lateral Silicon Controlled Rectifier Structure for ESD Protection
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Solution Overview
Problem
Existing lateral silicon controlled rectifier (LSCR) structures for electro-static discharge (ESD) protection in integrated circuits have inefficiencies due to higher threshold trigger voltages and larger chip area requirements, necessitating an improved design compatible with CMOS processes that is more efficient and compact.
Innovation Solution
A lateral silicon controlled rectifier structure is developed, featuring a P-type substrate with an N-well region, P+ and N+ doped regions, and a gate structure overlying the substrate, optimized with shallow trench isolation (STI) structures to reduce chip area and lower trigger voltages, allowing for efficient ESD current conduction without field oxide regions within the active area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If field oxide regions and N+ regions are used in LSCR structures, then ESD protection is provided, but chip area increases and trigger voltage increases
Solution Approach 1:
The patent removes field oxide regions and intermediate N+ regions from the LSCR structure, extracting unnecessary components that occupied chip area. The simplified structure uses only essential doped regions (P+, N+) separated by spacing distances, eliminating redundant elements while maintaining ESD protection functionality
Solution Approach 2:
The patent segments the LSCR structure into distinct functional regions with specific spacing distances between doped regions. The structure is divided into anode contact region, P+ region, N+ region, cathode contact region, and intermediate regions with controlled spacing, allowing optimization of each segment's contribution to ESD protection while minimizing total area
2Reliability
If field oxide regions and N+ regions are used in LSCR structures, then ESD protection is provided, but trigger voltage increases
Solution Approach 1:
The patent changes critical parameters including removing field oxide regions, adjusting doping concentrations in P+ and N+ regions, and optimizing spacing distances between regions. These parameter modifications directly reduce the trigger voltage by eliminating voltage drops across field oxide regions and intermediate N+ regions, allowing lower threshold triggering for ESD protection
3Reliability
If conventional LSCR structures are used, then ESD protection is achieved, but device complexity increases
Solution Approach 1:
The patent extracts and removes complex elements including field oxide regions, intermediate N+ regions, and multiple isolation structures. The resulting simplified LSCR structure contains only essential components (P+ region, N+ region, spacing distance, contact regions) connected in series, reducing manufacturing steps and structural complexity while preserving ESD protection function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The improved LSCR structure achieves lower threshold trigger voltages and enhanced efficiency in ESD protection, effectively reducing chip area usage and enabling reliable low ESD trigger levels without extensive overhead circuitry, thus safeguarding internal circuits from ESD damage.
Implementation Method 1
lateral silicon controlled rectifier (LSCR) structures are widely used in the semiconductor integrated circuits to protect CMOS devices against high voltages during an ESD event
Implementation Method 2
A gate structure overlying a portion of the P-type substrate between the first P+ doped region and the first N+ doped region
Data Source
AI summary
A lateral silicon controlled rectifier structure includes a P-type substrate; an N-well region in the P-type substrate; a first P+ doped region in the N-well region and being connected to an anode; a P-well region in the P-type substrate and bordering upon the N-well region; a first N+ doped region formed in the P-well region and separated from the first P+ doped region by a spacing distance, the first N+ doped region being connected to a cathode; and a gate structure overlying a portion of the P-type substrate between the first P+ doped region and the first N+ doped region.