Lateral Sub-Block Memory Programming With Staged Word-Line Ramping
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Solution Overview
Problem
Existing memory devices face inefficiencies in programming operations, particularly in lateral sub-block modes, leading to potential data upset in unprogrammed sub-blocks and increased error rates.
Innovation Solution
A programming technique involving a unique ramp down and ramp up scheme for word lines in lateral sub-block mode, where unselected word lines are sequentially ramped down and up in stages, with specific numbers of word lines ramped simultaneously, and the selected word line is ramped to negative and positive voltages to efficiently pre-charge channels without disturbing programmed data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional programming operations are used in lateral sub-block mode, then programming speed is maintained, but data upset occurs in unprogrammed sub-blocks leading to increased error rates
Solution Approach 1:
The memory block is divided into multiple sub-blocks (first sub-block and second sub-block) that can be independently programmed. The word lines are segmented into different groups (first group, second group, third group) that can be controlled separately. This segmentation allows the programming operation to be confined to specific sub-blocks, preventing data upset in unprogrammed areas while maintaining overall programming efficiency.
Solution Approach 2:
Different voltage conditions are applied to different regions of the memory block simultaneously. The selected sub-block receives programming voltages (Vpgm) on its word lines, while unselected sub-blocks maintain pass voltages (Vpass) or ground potential. This local differentiation ensures that programming effects are localized to the target sub-block, preserving data integrity in other regions.
2Loss of time
If all word lines are ramped down simultaneously, then pre-charge time is reduced, but coupling effects cause data upset in unselected word lines
Solution Approach 1:
The word lines are divided into multiple groups (first group, second group, third group) that are ramped down in different time stages. The first group is ramped down first, followed by the second group, and then the third group. This staged segmentation reduces the time that all word lines are simultaneously at high voltage, minimizing coupling effects while still achieving rapid pre-charge.
Solution Approach 2:
The word lines are ramped down in a specific sequence before the programming operation begins. By preliminarily reducing the voltage on unselected word lines in a staged manner, the patent prevents potential data upset from coupling effects before they can occur, ensuring data stability is maintained throughout the subsequent programming process.
3Productivity
If programming voltage is applied to selected word line immediately, then programming speed is maximized, but channels are not properly pre-charged leading to programming failures
Solution Approach 1:
Before applying the programming voltage to the selected word line, the patent performs a preliminary pre-charge operation where all word lines are sequentially ramped down to ground potential in stages. This preliminary action ensures that the channels are properly prepared and free from residual charges that could interfere with programming, while the staged approach keeps the pre-charge time minimal.
Solution Approach 2:
The patent employs dynamic voltage control where the voltage on word lines changes over time in a coordinated sequence. The pre-charge phase dynamically ramps down all word lines in stages, then dynamically transitions to the programming phase where the selected word line receives Vpgm while unselected word lines maintain appropriate voltages. This dynamic control ensures both proper channel preparation and high programming speed.
Data Source
AI summary
The memory device includes a memory block with an array of memory cells that are arranged in a plurality of word lines and that are divided into at least two laterally divided sub-blocks. Control circuitry programs the memory cells of one of the sub-blocks in a plurality of program loops. During at least one of the program loops, the control circuitry ramps down a selected word line being programmed from a reference voltage. After beginning to ramp down the selected word line from the reference voltage, the control circuitry sequentially ramps down a plurality of unselected word lines from pass voltages from nearest the selected word line to the opposite ends of the memory block. Then, the control circuitry ramps up a plurality of unselected word lines that are distant from the selected word line. Next, the control circuitry ramps up the selected word line to a programming voltage.