Lateral Super Junction Device With Avalanche Clamp Diode
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Solution Overview
Problem
Conventional semiconductor power devices with super-junction structures face manufacturability difficulties due to complex and costly processes, particularly in achieving high-density alternately doped columns, which affect on-resistance and breakdown voltage performance.
Innovation Solution
A lateral super-junction structure is implemented with a P-epitaxial layer over an N substrate, featuring deep N-type source and drain columns and a P+ gate column, along with an N+-P-P+ gate-drain avalanche clamp diode to enhance breakdown voltage and current spreading, and integrating a low voltage MOSFET for cascode connection to achieve normally-off operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vertical super junction structure with high-density alternately doped columns is implemented, then on-resistance is reduced and breakdown voltage is improved, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent transitions from a vertical super junction structure to a lateral super junction structure. In the lateral configuration, the alternating n-type and p-type doped columns are arranged horizontally rather than vertically stacked, allowing current to flow laterally through the super junction region. This dimensional change simplifies manufacturing by eliminating the need for complex vertical alignment and reduces the number of epitaxial growth steps while maintaining the charge-balanced field effect that enables high breakdown voltage and low on-resistance.
Solution Approach 2:
The patent inverts the conventional vertical super junction architecture by placing the drain region at the substrate level rather than at the surface. The deep drain trench extends through the P-epitaxial layer to contact the N+ substrate, creating a bottom-drain configuration. This inversion separates the high-current drain terminal from the gate and source terminals on the surface, improving current spreading and reducing parasitic inductance while simplifying the overall device structure.
2Reliability
If deep drain trench is formed to contact N+ substrate, then substrate blocking voltage is increased and current spreading is improved, but manufacturing steps increase
Solution Approach 1:
The patent combines multiple functions into the deep drain trench structure. The same trench that provides the low-impedance path to the N+ substrate also serves as the region where the drain terminal is formed and where the parasitic NPN transistor suppression is achieved through appropriate doping. This merging of functions reduces the need for separate structural elements and simplifies the manufacturing process despite the deep trench requirement.
3Reliability
If avalanche clamp diode is formed between gate and drain, then UIS performance is improved and device robustness is enhanced, but device complexity increases
Solution Approach 1:
The P+ gate column serves multiple functions: it provides the gate control function for the JFET, forms the avalanche clamp diode with the N+ substrate to protect against UIS damage, and acts as one of the alternately doped columns in the lateral super junction structure. This multi-functionality reduces overall device complexity by eliminating the need for separate avalanche diode structures while achieving robust UIS performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves manufacturability, reduces on-resistance, increases breakdown voltage, and enhances unclamped inductive switching performance while maintaining efficient current distribution and robustness against avalanche breakdown.
Implementation Method 1
an N+-P-P+ gate-drain avalanche clamp diode is formed from the N+ drain substrate to the P-epitaxial to the P+ gate column to provide a rugged high voltage diode that diverts the avalanche current away from the superjunction layers of this device
Data Source
AI summary
A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.