Lateral Superjunction GaN Selective Epitaxy Defect Trapping
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Solution Overview
Problem
Current power electronics devices struggle to achieve high breakdown voltages at low on-resistances due to material defects and the inability to effectively use inexpensive substrates like silicon or sapphire for lateral superjunction GaN devices.
Innovation Solution
The process involves selective epitaxy to form alternating p/n layers on a substrate, using techniques like patterning, etching, and regrowing ohmic contact regions, which reduces defects and enhances device performance by trapping defects in small openings, allowing for the creation of high-quality lateral superjunctions on silicon or sapphire substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional epitaxy methods are used to grow GaN layers on silicon or sapphire substrates, then manufacturing cost is reduced, but material defects increase and device performance deteriorates
Solution Approach 1:
The patent segments the epitaxial growth process into multiple stages: initial nucleation layer formation, intermediate buffer layer growth, and final device layer deposition. Each stage uses optimized growth conditions and intermediate treatments to prevent defect propagation from the substrate to the device layers, enabling low-cost substrate use without sacrificing device performance
Solution Approach 2:
The patent applies preliminary actions by forming nucleation layers and buffer layers before the main device layers. These preliminary layers are specifically designed to trap defects and create a high-quality growth template, preventing substrate defects from affecting the final device performance while maintaining cost-effectiveness
2Reliability
If lateral superjunction structures are fabricated to achieve high breakdown voltages, then device performance improves, but manufacturing complexity increases
Solution Approach 1:
The patent merges the formation of alternating p-type and n-type layers into a single selective epitaxy process rather than requiring separate fabrication steps. This integration achieves the complex lateral superjunction structure needed for high breakdown voltages while reducing manufacturing complexity through process consolidation
Solution Approach 2:
The patent applies local quality by using selective epitaxy to create alternating doped and undoped regions with precise spatial control. Each region is grown with specific doping conditions tailored to its function, enabling high breakdown voltage performance through optimized local material properties without increasing overall manufacturing complexity
3Manufacturing precision
If defect trapping techniques are used during epitaxy, then material quality improves, but process time increases
Solution Approach 1:
The patent maintains continuous epitaxial growth throughout the defect trapping process, avoiding interruptions or separate treatment steps. The defect trapping mechanism operates continuously during layer formation, improving material quality without adding significant process time through uninterrupted growth cycles
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in power electronics with higher breakdown voltages and lower on-resistances, improving device efficiency and reducing manufacturing costs while increasing yield and reliability.
Implementation Method 1
performing selective epitaxy to form alternating p/n layers in-situ
Implementation Method 2
trapping defects that occur during growth in the opening
Data Source
AI summary
A lateral superjunction includes a substrate layer, a selective epitaxy layer deposited on the substrate layer, a trench formed into the selective epitaxy layer to expose a portion of the substrate layer, a first layer of semiconductor deposited in the trench, a second layer of semiconductor deposited adjacent to the first layer, and a first end layer of semiconductor deposited adjacent to the first layer of semiconductor and a second end layer of semiconductor deposited adjacent to the second layer of semiconductor.