Lateral Test Pin Assembly for Vertical Semiconductor Die Testing
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Solution Overview
Problem
Existing methods for testing semiconductor dies with vertical transistors, such as IGBT transistors, face challenges in efficiently connecting and testing these devices without incurring high parasitic inductance, especially when trying to connect test apparatus to the lower main face, which can lead to current limitations and inefficiencies.
Innovation Solution
A method and apparatus that utilize a lateral test pin arrangement with an auxiliary semiconductor die to create a conductive path between the upper and lower main faces, allowing for synchronized control signals to be applied, thereby eliminating the need for direct electrical connection to the lower main face and minimizing parasitic inductance, using a test pin assembly and a control unit to generate and supply control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If direct electrical connection to the lower main face is made, then testing of vertical transistors is enabled, but parasitic inductance increases and current capability is limited
Solution Approach 1:
The patent transitions from vertical connection (through the lower main face) to lateral connection (through the upper main face). The test pin assembly connects to contact elements on the upper main face, changing the connection dimension from vertical to horizontal, thereby avoiding the parasitic inductance associated with vertical wire connections to the lower face.
Solution Approach 2:
The patent introduces contact elements on the upper main face as intermediary connection points. These contact elements serve as mediators between the test pin assembly and the vertical transistor structure, enabling testing without direct connection to the lower main face and thus avoiding parasitic inductance.
2Reliability
If vertical transistor structure is tested, then functionality is verified, but connection complexity increases due to access to both main faces
Solution Approach 1:
The patent combines multiple connection functions into a single test pin assembly that connects to the upper main face. Instead of requiring separate connections to both upper and lower faces, the assembly integrates all necessary electrical connections through the upper face contact elements, simplifying the overall connection structure.
Solution Approach 2:
The patent reconfigures the connection architecture from a three-dimensional approach (accessing both upper and lower faces) to a two-dimensional approach (all connections through the upper main face plane), thereby reducing connection complexity while maintaining full testing capability.
3Loss of time
If wafer-level testing is performed, then early defect identification is achieved, but testing efficiency is reduced due to connection limitations
Solution Approach 1:
The patent enables testing to be performed at the wafer level before dicing, allowing early defect identification. The test pin assembly is designed to work with wafer-mounted dies, facilitating preliminary testing actions that catch defects early in the fabrication process, thereby reducing waste and improving yield.
Solution Approach 2:
The patent replaces complex mechanical connection systems (wire bonds, probes to lower face) with a simplified lateral connection system using contact elements on the upper face. This substitution maintains testing efficiency while enabling wafer-level processing, as the lateral connection approach is more compatible with automated wafer handling and testing equipment.
Data Source
AI summary
A method for testing semiconductor dies includes: providing a test apparatus; providing an electrically conductive carrier; providing a semiconductor substrate having a first main face, a second main face opposite to the first main face, and a plurality of semiconductor dies, the semiconductor dies including a first contact element on the first main face and a second contact element on the second main face; placing the semiconductor substrate on the carrier with the second main face facing the carrier; electrically connecting the carrier to a contact location disposed on the first main face; and testing a first semiconductor die of the plurality of semiconductor dies by electrically connecting the test apparatus with the first contact element of the first semiconductor die and the contact location.