Lateral Thin Film Varistor Low Temperature Fabrication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional ESD protection devices, such as silicon controlled rectifier (SCR) and generic transient voltage suppression (TVS) devices, are not robust enough for high current transients in IC chips with thin film substrates, which are sensitive to electrostatic discharge (ESD) and can be damaged by high temperature sintering during vertical varistor fabrication.
Innovation Solution
A laterally configured thin film varistor is fabricated using low temperature sputtering techniques followed by low temperature annealing, allowing for minimal vertical space usage and avoiding damage to adjacent semiconductor components, with a continuous layer of alternating metal oxide regions between laterally spaced electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high temperature sintering is used to fabricate vertical varistors, then the varistor can achieve proper electrical characteristics, but adjacent semiconductor components are damaged
Solution Approach 1:
The patent changes the temperature parameter from conventional high temperature sintering (900-1100°C) to low temperature processing (room temperature to 400°C). This parameter change enables the formation of functional metal oxide varistor layers without damaging adjacent semiconductor components, resolving the contradiction between achieving proper electrical characteristics and preventing component damage
Solution Approach 2:
The patent replaces the conventional thermal sintering mechanism with alternative deposition techniques such as sputtering, chemical vapor deposition (CVD), or atomic layer deposition (ALD). These methods substitute the high-temperature thermal field with controlled deposition processes that can form metal oxide layers at low temperatures, thereby protecting adjacent components while still achieving functional varistor characteristics
2Device complexity
If conventional vertical varistor configuration is used, then the device structure is simple, but the vertical space requirement increases and integration density decreases
Solution Approach 1:
The patent transitions from a vertical varistor configuration to a lateral configuration, changing the spatial dimension in which the varistor function is implemented. The metal oxide layers are deposited laterally between adjacent conductive lines or vias on the same or adjacent metal layers, converting the vertical space requirement into a lateral layout that utilizes available planar space more efficiently, thereby increasing integration density
3Reliability
If SCR or TVS devices are used for ESD protection, then the protection mechanism is established, but the devices are not robust enough for high current transients in thin film substrates
Solution Approach 1:
The patent employs composite metal oxide materials, specifically combinations of zinc oxide (ZnO) with other metal oxides such as bismuth oxide (Bi2O3), calcium oxide (CaO), or magnesium oxide (MgO). These composite materials provide superior robustness against high current transients compared to conventional SCR or TVS devices, while being compatible with thin film substrate processing. The composite structure enables the varistor to handle high surge currents effectively
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The lateral thin film varistor effectively handles higher voltage surges and maintains stability at elevated temperatures, providing robust ESD protection without damaging adjacent components, and can be easily integrated into compact IC chip designs.
Implementation Method 1
forming a continuous layer comprising alternating regions of a first metal oxide layer and a second metal oxide layer between two laterally spaced electrodes using a low temperature sputtering process
Implementation Method 2
followed by a low temperature annealing process
Data Source
AI summary
A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may include a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.


