Lateral Transistor Buffer Layer Segmentation for Snapback Robustness

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Solution Overview

Problem

Lateral transistor devices face challenges in maintaining robustness against snapback, which restricts operating current and can lead to device failure due to snapback occurring at too low current densities, especially in high voltage and high current applications.

Innovation Solution

Incorporating a buffer layer arrangement with a second buffer layer between the first buffer layer and the contact layer, where the doping concentration of the second buffer layer is between that of the first buffer layer and the contact layer, enhances the snapback robustness by reducing electrical field strength towards the contact layer, preventing snapback conditions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If a lateral transistor device is designed for high voltage and high current applications, then the operating current range is extended, but snapback occurs at too low current densities leading to device failure

Engineering Contradiction:
Improveoperating current rangeVSAvoidsnapback robustness
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The buffer layer is divided into two distinct layers (first buffer layer and second buffer layer) with different doping concentrations. The first buffer layer has a lower doping concentration while the second buffer layer has a higher doping concentration, creating a gradient structure that segments the electrical field distribution and prevents snapback occurrence

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the buffer layer arrangement have different doping concentrations tailored to specific functional requirements. The first buffer layer region is optimized for field distribution while the second buffer layer region is optimized for snapback prevention, creating local quality variations that solve the contradiction

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed solution significantly increases the critical current at which snapback occurs, enhancing the robustness of the lateral transistor device and preventing potential device destruction, thereby ensuring reliable operation in high voltage and high current applications.

Implementation Method 1

the doping concentration of the second buffer layer is in a range between a doping concentration of the first buffer layer and a doping concentration of the contact layer

Methodology Applied
Scientific EffectElectrical field distribution: Electric Field

Implementation Method 2

The first buffer layer, the second buffer layer and the contact layer have a same doping type

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentEP3696863B1Lateral transistor device
Publication Date: 2021.10.13 INFINEON TECH AUSTRIA AG
  • EP3696863B1 patent drawingFigure 1~2B
  • EP3696863B1 patent drawingFigure 3~4
  • EP3696863B1 patent drawingFigure 5A~5B

AI summary

A lateral transistor device (400; 800; 900; 1000) comprises a layer stack (410; 810; 910; 1010) with a plurality of first semiconductor layers (412; 812; 912; 1012) of a first doping type and a plurality of second semiconductor layers (414; 814; 914; 1014) of a second doping type complementary to the first doping type. The lateral transistor device (400; 800; 900; 1000) further comprises a source region (420; 820; 1020), a drain region (424; 824; 1024) spaced apart from the source region (420; 820; 1020) in a first lateral direction of the lateral transistor device, at least one gate region (428; 828; 1028) arranged between the source region (420; 820; 1020) and the drain region (424; 824; 1024), a buffer layer arrangement (430, 450; 830, 850; 930, 950; 1030, 1050), and a contact layer (440; 840; 940; 1040). The buffer layer arrangement (430, 450; 830, 850; 930, 950; 1030, 1050) is arranged between the contact layer (440; 840; 940; 1040) and at least parts of the layer stack (410; 810; 910; 1010), the source region (420; 820; 1020) and the drain region (424; 824; 1024) in a vertical direction of the lateral transistor device. The buffer layer arrangement (430, 450; 830, 850; 930, 950; 1030, 1050) comprises a first buffer layer (430; 830; 930; 1030) and a second buffer layer (450; 850; 950; 1050), the second buffer layer (450; 850; 950; 1050) being arranged between the first buffer layer (430; 830; 930; 1050) and the contact layer (440; 840; 940; 1040). The first buffer layer (430; 830; 930; 1030), the second buffer layer (450; 850; 950; 1050) and the contact layer (440; 840; 940; 1040) have a same doping type, and a doping concentration of the second buffer layer (450; 850; 950; 1050) is in a range between a doping concentration of the first buffer layer (430; 830; 930; 1030) and a doping concentration of the contact layer (440; 840; 940; 1040).