Lateral Transistor ESD Protection With Wall-Penetrating Base Region
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Solution Overview
Problem
Current electrostatic discharge (ESD) protection devices in integrated circuits face challenges in achieving a low trigger voltage, suitable holding voltage, and low dynamic resistance, which affects their performance in protecting against ESD-induced malfunctions.
Innovation Solution
The proposed solution involves a device with a substrate and a peripheral insulation wall, where the base region of a lateral transistor penetrates into the wall over a specific distance, and includes Zener diodes connected to the transistor's collector and emitter regions, optimizing the holding voltage and blocking voltage to enhance ESD protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the base region stops before the wall, then the manufacturing process is simpler, but the holding voltage and blocking voltage cannot be optimized effectively
Solution Approach 1:
The base region is extended in a new dimension by penetrating through the peripheral insulation wall, transforming from a conventional planar structure to a three-dimensional structure that extends laterally beyond the wall boundary. This dimensional change enables simultaneous optimization of holding voltage and blocking voltage while maintaining manufacturing feasibility through standard semiconductor fabrication processes.
Solution Approach 2:
The base region penetration depth is optimized locally at different positions: it penetrates through the peripheral insulation wall to achieve optimal holding voltage (greater than 5V) and blocking voltage (less than 7V), while the penetration distance is controlled to be between 20%-50% of the base region length to balance performance and manufacturing complexity.
2Reliability
If the base region penetrates deeply into the wall, then the holding voltage and blocking voltage are optimized, but the manufacturing precision requirements increase
Solution Approach 1:
The penetration distance of the base region is optimized to specific parameter ranges (20%-50% of the base region length, with 30% being preferred) to achieve optimal holding voltage greater than 5V and blocking voltage less than 7V. These parameter specifications provide clear manufacturing targets that balance performance optimization with fabrication capability.
3Reliability
If the trigger voltage is lowered to protect the circuit, then the protection effectiveness increases, but unwanted triggering during normal operation occurs
Solution Approach 1:
The peripheral insulation wall structure with selective base region penetration creates localized electrical characteristics that enable different voltage thresholds for different operating conditions. The wall structure with specific penetration depth (20%-50% of base region length) provides electrical isolation that prevents unwanted triggering during normal operation while allowing effective protection during ESD events.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a holding voltage greater than 5 V and a blocking voltage less than 7 V, effectively protecting circuits against ESD while maintaining low dynamic resistance, thus improving the overall performance of ESD protection.
Implementation Method 1
Electrostatic discharges (ESD) occurring in an unprotected integrated circuit can produce undesirable effects, which most of the time lead to deterioration of the constituent elements of this circuit.
Implementation Method 2
at least one lateral transistor (390, 370, 380) of which a base region (390) penetrates inside a peripheral insulation wall (340)
Data Source
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AI summary
The present description relates to an electronic device (100) comprising a substrate (300) having: a box (330); a peripheral insulation wall (340) surrounding the box (330); and at least one lateral bipolar transistor (500) made in the box (330), of which a base region (390) extends under parallel collector and emitter regions (370, 372, 374, 380, 382), the wall (340) being widened in a first direction (X) parallel to the collector and emitter regions (370, 372, 374, 380, 382) such that the base region (390) penetrates inside the wall (340).