Lateral Power Transistor Package Layout for Low Common Source Inductance
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Solution Overview
Problem
Conventional transistor packages suffer from parasitic elements that limit switching performance, particularly due to parasitic common source inductance, and the inclusion of a source Kelvin pin degrades package inductance and resistance.
Innovation Solution
A transistor package design featuring a multi-layer laminate substrate with structured metal layers and vias that separate the drain-source and gate-source current paths, allowing for a gate-source current path on one layer and a drain-source current path on multiple layers, thereby reducing parasitic inductance and enabling fast switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a source Kelvin pin and source Kelvin connection are added to provide a reference potential for gate driving voltage, then the gate driving voltage reference is improved, but the package inductance and package resistance are degraded
Solution Approach 1:
The patent extracts the source sense function from a separate Kelvin pin configuration and integrates it into the multi-layer substrate structure. The source sense terminal is directly connected to the source electrode through dedicated vias and metal traces on the substrate, eliminating the need for an external Kelvin pin while maintaining the reference potential function. This extraction approach removes the harmful inductance and resistance associated with traditional Kelvin pin connections.
Solution Approach 2:
The patent transitions from a two-dimensional planar connection (single-layer substrate with external Kelvin pin) to a three-dimensional multi-layer structure. By routing the source sense connection through vertical vias across multiple substrate layers and using dedicated metal traces on different layers, the patent creates a low-inductance path that exploits the third dimension (vertical depth) to minimize parasitic effects while providing the reference potential.
2Temperature
If conventional leadless packages and clips are used to reduce device parasitics and improve thermal behavior, then thermal performance is improved, but parasitic common source inductance remains and limits switching performance
Solution Approach 1:
The patent segments the current paths into distinct routes on different substrate layers. The source sense current (gate driving reference) is separated from the drain-source power current by routing them through different vias and metal traces on the multi-layer substrate. This segmentation prevents the superposition of currents that creates common source inductance, while still providing excellent thermal pathways through the substrate's thermal vias and heat sink structure.
Solution Approach 2:
The multi-layer substrate acts as an intermediary structure that simultaneously provides electrical connection and thermal management functions. The substrate's internal vias and metal layers serve as intermediate pathways that separate sense and power currents electrically while maintaining thermal coupling to the heat sink, resolving the conflict between reducing parasitic inductance and improving thermal behavior.
3Speed
If a multi-layer laminate substrate with separated current paths is used, then parasitic inductance is reduced and switching speed is improved, but device complexity increases
Solution Approach 1:
The multi-layer substrate performs multiple functions simultaneously: it provides electrical connection between chip terminals and package leads, separates sense and power current paths to reduce parasitic inductance, provides thermal management pathways through thermal vias, and offers mechanical support. By consolidating these functions into a single multi-layer substrate structure rather than using separate components, the patent reduces overall device complexity while achieving fast switching performance.
Data Source
Figure 1~2B
Figure 3~5B
Figure 6A~9B
AI summary
A transistor package for a power transistor chip includes the power transistor chip having a first side and a second side opposite the first side. The first side comprises a source electrode metallization, a drain electrode metallization and a gate electrode metallization. The package further includes a multi-layer laminate substrate to which the power transistor chip is connected. The multi-layer laminate substrate comprises a first structured metal layer facing the first side of the power transistor chip and being electrically connected to the source electrode metallization, the drain electrode metallization and the gate electrode metallization, a second structured metal layer comprising a source package terminal pad, a source sense package terminal pad, a drain package terminal pad and a gate package terminal pad, at least one insulating layer disposed between the first structured metal layer and the second structured metal layer, and a plurality of vias running through the insulating layer and connecting segments of the first structured metal layer to the terminal pads of the second structured metal layer. The first structured metal layer, the second structured metal layer and the plurality of vias are designed such that a gate-source current path between the power transistor chip and the source sense package terminal pad is provided only on one of the first and second structured metal layers while a drain-source current path between the source electrode metallization of the power transistor chip and the source package terminal pad is at least on the other structured metal layer of the multi-layer laminate substrate.