Lateral Power Transistor Package Layout for Low Parasitic Switching
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Solution Overview
Problem
Conventional transistor packages face challenges in reducing device parasitics, particularly drain/source inductance, for fast switching and improving thermal behavior, while also aiming for higher efficiency, increased power density, and lower switching losses.
Innovation Solution
A transistor package design featuring a semiconductor transistor chip with load electrodes and a leadframe, where terminals are aligned in a specific configuration to minimize parasitics and facilitate thermal connectivity, and a flip-chip structure for mounting on a circuit board, allowing for low stray inductance and efficient wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If conventional packages are used, then manufacturing is simpler, but device parasitics (drain/source inductance) are higher
Solution Approach 1:
The package structure is segmented into distinct functional regions: a first region for the drain terminal and a second region for the source terminal, with the gate terminal positioned between them. This segmentation allows optimization of current paths and reduction of parasitic inductance by separating high-current drain and source connections while maintaining compact overall dimensions.
Solution Approach 2:
The patent transitions from conventional planar terminal arrangements to a three-dimensional configuration where terminals are positioned at different locations on the package body. The drain terminal is exposed at a first location, the source terminal at a second location, and the gate terminal at a third location between them, creating optimized current paths in multiple spatial dimensions that reduce parasitic effects.
2Object-generated harmful factors
If leadless packages are used, then parasitics are reduced, but manufacturing complexity increases
Solution Approach 1:
The package design incorporates multiple terminal exposure configurations that can accommodate different mounting and connection requirements. The drain, source, and gate terminals are exposed at strategically positioned locations that allow for versatile PCB mounting options and wiring configurations, making the package universally applicable to various circuit designs while maintaining low parasitic characteristics.
3Object-generated harmful factors
If clips are used for connecting load electrodes, then parasitics are reduced, but device complexity increases
Solution Approach 1:
The package structure merges the terminal connection functions into an integrated leadframe assembly where the drain terminal, source terminal, and gate terminal are all part of a unified structure. This eliminates the need for separate clips or additional connection components, reducing overall device complexity while maintaining low parasitic inductance through optimized current paths.
Data Source
AI summary
A transistor package includes a semiconductor transistor chip having opposite first and second surfaces, one or a plurality of first load electrodes, one or a plurality of second load electrodes, and a control electrode on the first surface. A leadframe faces the first surface of the semiconductor transistor chip and includes a first terminal, a second terminal, and a control terminal of the package which are exposed at a bottom of the package. The first terminal is electrically coupled to the first load electrode(s). The second terminal is electrically coupled to the second load electrode(s). The control terminal is electrically coupled to the control electrode. The first terminal is aligned with a first side of the package. The second terminal is aligned with a second side opposite the first side. The control terminal is aligned with a third side of the package which connects between the first and second sides.