Lateral Transistor Superjunction Drift Layer Design
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Solution Overview
Problem
Power transistors in automotive and industrial electronics require low on-state resistance while maintaining high voltage blocking capability, which existing designs struggle to achieve effectively, especially in lateral MOS transistors with superjunction layer stacks.
Innovation Solution
A semiconductor device with a source and drain region of a first conductivity type, a drift layer of the same conductivity type, and a compensation layer of a second conductivity type, where the drain region is electrically connected to the drift layer, and a connection region of the second conductivity type extending into the substrate, with a buried semiconductor portion of the first conductivity type beneath the layer stack, having a soft doping profile to enhance current blocking characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the drift layer is fully depleted in off-state to prevent current flow, then voltage blocking capability is improved, but on-state resistance increases
Solution Approach 1:
The patent employs superjunction layer stacks with alternating n-type and p-type doping layers, where the doping concentrations and thicknesses are precisely controlled to achieve optimal balance. The n-type drift layers provide voltage blocking when depleted, while the p-type compensation layers reduce the net doping to enable lower on-state resistance. This parameter optimization resolves the contradiction between voltage blocking capability and on-state resistance.
Solution Approach 2:
The invention uses a composite structure of alternating n-type and p-type semiconductor layers forming a superjunction stack. This composite material approach allows the drift region to exhibit both high voltage blocking capability (when depleted) and low on-state resistance through the compensating effect of opposite polarity dopants, effectively resolving the technical contradiction.
2Loss of energy
If superjunction layer stacks are used to reduce on-state resistance, then current conduction is improved, but manufacturing complexity increases
Solution Approach 1:
The drift region is segmented into multiple alternating n-type and p-type layers forming a superjunction stack. This segmentation allows each layer to contribute to either voltage blocking or resistance reduction, achieving low on-state resistance while maintaining a manageable structure through repetitive unit cells.
Solution Approach 2:
By optimizing the thickness and doping concentration parameters of each layer in the superjunction stack, the patent achieves low on-state resistance with a standardized repeating structure. The parameters are tuned so that the layers can be manufactured using conventional semiconductor processes, reducing the impact of complexity.
3Reliability
If the buried semiconductor portion has a soft doping profile, then current blocking characteristics are improved, but manufacturing precision requirements increase
Solution Approach 1:
The buried semiconductor portion is designed with a soft doping profile where the doping concentration gradually decreases from the interface toward the bulk. This gradual transition (parameter variation) smooths the electric field distribution, improving current blocking characteristics while the profile can be achieved through controlled diffusion processes that are well-established in semiconductor manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor device achieves reduced on-state resistance while maintaining high voltage blocking capability by fully depleting the drift layers in the off-state, preventing current flow and improving current blocking characteristics.
Implementation Method 1
fully depleting the drift layers in the off-state, preventing current flow
Implementation Method 2
buried semiconductor portion of the first conductivity type beneath the layer stack, having a soft doping profile
Data Source
AI summary
A semiconductor device includes a source region and a drain region of a first conductivity type. The source region and the drain region are arranged in a first direction parallel to a first main surface of a semiconductor substrate. The semiconductor device further includes a layer stack having a drift layer of the first conductivity type and a compensation layer of a second conductivity type. The drain region is electrically connected with the drift layer. The semiconductor device also includes a connection region of the second conductivity type extending into the semiconductor substrate, the connection region being electrically connected with the compensation layer, wherein the buried semiconductor portion does not fully overlap with the drift layer.