Lateral Through Silicon Via for Flexible 3D Chip Stacking
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Solution Overview
Problem
Current Through Silicon Via (TSV) technologies are limited to vertical configurations, restricting the use of three-dimensional stacked structures with multiple stacking directions, which hampers the applicability and efficiency of interconnection between chips.
Innovation Solution
A semiconductor structure and manufacturing method that incorporates lateral TSVs, allowing for the formation of a patterned conductive layer connected to contact pads on the chip's active side and embedded in the chip's lateral side, enabling three-dimensional stacked chip packages with increased signal transmission routes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If vertical TSV configuration is used, then interconnection speed is improved, but stacking direction flexibility is limited
Solution Approach 1:
The patent introduces lateral TSVs that extend horizontally along the lateral side of the chip substrate, complementing traditional vertical TSVs. This dimensional expansion from purely vertical to including lateral pathways enables three-dimensional stacked structures with multiple stacking directions, resolving the contradiction between maintaining fast interconnection speed and achieving stacking flexibility
2Adaptability or versatility
If three-dimensional stacked structure with multiple stacking directions is implemented, then stacking direction flexibility is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the TSV configuration into distinct vertical and lateral components. Vertical TSVs provide primary interconnection pathways while lateral TSVs extend from the lateral side of the chip substrate to enable additional stacking directions. This segmentation allows each TSV type to be manufactured and optimized independently, reducing overall manufacturing complexity while achieving three-dimensional stacking flexibility
3Adaptability or versatility
If lateral TSV is added to the chip structure, then stacking direction flexibility is improved, but device complexity increases
Solution Approach 1:
The patent merges vertical and lateral TSV configurations into a unified chip structure. The lateral TSV extends from the lateral side of the chip substrate and connects to the vertical TSV network, creating an integrated three-dimensional interconnection system. This merging approach achieves stacking direction flexibility while consolidating the TSV architecture into a cohesive device structure
Data Source
AI summary
The present invention provides a semiconductor structure having a lateral TSV and a manufacturing method thereof. The semiconductor structure includes a chip having an active side, a back side disposed opposite to the active side, and a lateral side disposed between the active side and the back side. The chip further includes a contact pad, a lateral TSV and a patterned conductive layer. The contact pad is disposed on the active side. The lateral TSV is disposed on the lateral side. The patterned conductive layer is disposed on the active side and is electrically connected to the lateral TSV and the contact pad.