Lateral TVS With Deep Isolation Trenches For Low Capacitance
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Solution Overview
Problem
Traditional transient voltage suppressors (TVS) face a challenge in reducing input capacitance for high-speed interface applications without increasing device size, as larger sizes are required for better ESD performance, leading to high input capacitance.
Innovation Solution
A lateral transient voltage suppressor with ultra low capacitance is achieved by using deep isolation trenches to separate doped wells in the substrate, incorporating a diode cascade structure with specific conductivity type arrangements and deep isolation trenches to minimize capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the TVS device size is increased to improve ESD performance, then the ESD protection capability is improved, but the input capacitance increases
Solution Approach 1:
The patent divides the TVS device into multiple independent doped wells (first conductivity type lightly doped well and second conductivity type lightly doped well) separated by deep isolation trenches. This segmentation isolates the electrical characteristics of each well, preventing capacitance coupling between adjacent regions while maintaining the overall ESD protection function through the series-connected diode cascade structure.
Solution Approach 2:
The patent applies different doping concentrations and conductivity types to specific local regions (lightly doped vs. heavily doped areas, first conductivity type vs. second conductivity type) to optimize both ESD performance and capacitance characteristics. The deep isolation trenches are strategically positioned between lightly doped wells to achieve ultra-low capacitance in critical signal paths while maintaining robust ESD protection in other regions.
2Quantity of substance
If the device size is reduced to improve signal performance, then the input capacitance is reduced, but the ESD protection capability deteriorates
Solution Approach 1:
The patent transitions from planar TVS structures to a three-dimensional architecture with deep isolation trenches extending vertically into the substrate. This vertical dimension provides effective electrical isolation between adjacent doped wells, enabling ultra-low capacitance performance while maintaining compact horizontal footprint for high-speed interface applications.
Solution Approach 2:
The patent employs a composite structure combining multiple semiconductor materials with different conductivity types (P-type and N-type substrates, lightly doped and heavily doped regions) arranged in a diode cascade configuration. This composite architecture achieves both low capacitance and high ESD protection capability through the synergistic interaction of different material properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces input capacitance, enhancing signal performance for high-speed interface applications while maintaining adequate ESD protection without increasing device size.
Implementation Method 1
after well drive-in process, the dosage of the P-type lightly doped well 24 and the N-type lightly doped well 30 will be still affected by the P-type doped well 38 and increased, which results in high input capacitance of the traditional TVS
Data Source
AI summary
A lateral transient voltage suppressor with ultra low capacitance is disclosed. The suppressor comprises a first conductivity type substrate and at least one diode cascade structure arranged in the first conductivity type substrate. The cascade structure further comprises at least one second conductivity type lightly doped well and at least one first conductivity type lightly doped well, wherein there are two heavily doped areas arranged in the second conductivity type lightly doped well and the first conductivity type lightly doped well. The cascade structure neighbors a second conductivity type well, wherein there are three heavily doped areas arranged in the second conductivity type well. The suppressor further comprises a plurality of deep isolation trenches arranged in the first conductivity type substrate and having a depth greater than depths of the second conductivity type lightly doped well, the second conductivity type well and the first conductivity type lightly doped well. Each doped well is isolated by trenches.