Laterally Insulated IC Chips via Plasma Etching
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Solution Overview
Problem
Existing methods for fabricating laterally insulated integrated circuit chips require multiple processing steps, including deep reactive ion etching and chemical cleaning, which can lead to contamination and inefficiencies.
Innovation Solution
A method involving successive steps of ion etching using sulfur hexafluoride plasma and passivation using octafluorocyclobutane plasma to form peripheral trenches, with the resulting insulating layer of polyfluoroethene retained on the lateral walls, allowing for wafer thinning without prior removal, thereby reducing processing steps and maintaining the polymer layer for insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If deep reactive ion etching process is used to form trenches, then trench depth is achieved, but polymer layer is formed on trench walls requiring chemical cleaning
Solution Approach 1:
The patent converts the harmful polymer layer formed during etching into a beneficial insulating layer. Instead of removing the polymer through chemical cleaning, the process retains it and applies additional passivation steps to enhance its insulating properties, thereby eliminating a processing step while achieving the desired lateral insulation function.
Solution Approach 2:
The patent changes the parameters of the etching process by using specific gas compositions (SF6 with oxygen or carbon dioxide) and controlling etching conditions to modify the properties of the polymer layer formed on trench walls. This transforms the polymer from a contaminant into a functional insulating layer with controlled thickness and electrical properties.
2Object-generated harmful factors
If chemical cleaning step is added to remove polymer layer, then contamination is reduced, but number of processing steps increases
Solution Approach 1:
The patent eliminates the chemical cleaning step by converting the polymer layer from a harmful contaminant into a useful insulating layer. Additional passivation steps are applied to enhance the insulating properties of the retained polymer, thereby reducing process complexity while maintaining or improving electrical insulation performance.
Solution Approach 2:
The patent merges the functions of the polymer layer formation and the insulating layer formation into a single integrated process. The polymer layer formed during etching serves as the base for the final insulating layer, combining what were previously separate steps (etching followed by cleaning, then separate insulation deposition) into a more efficient sequence.
3Reliability
If insulating layer is deposited conformally in trench, then lateral insulation is achieved, but processing time increases
Solution Approach 1:
The patent performs preliminary passivation actions during the etching process itself, where the polymer layer is formed on the trench walls as the etching progresses. This preliminary formation of the insulating layer occurs concurrently with trench creation rather than as a separate post-etching step, thereby reducing total processing time while ensuring proper insulation.
Solution Approach 2:
The patent maintains continuous useful action by keeping the polymer layer in place and building upon it with additional passivation steps, rather than removing it and starting fresh with a separate insulation deposition process. This continuous approach to insulating layer formation reduces interruptions and shortens overall processing time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes processing steps, eliminates the need for chemical cleaning, and effectively insulates the lateral faces of integrated circuit chips, enhancing the fabrication efficiency and reducing contamination risks.
Implementation Method 1
forming is accomplished by repeating successive steps of ion etching using a sulfur hexafluoride plasma
Implementation Method 2
passivating using an octafluorocyclobutane plasma such that, upon completion of the step of forming the peripheral trenches, lateral walls of the peripheral trenches are covered by an insulating layer made of a polyfluoroethene
Data Source
AI summary
Laterally insulated integrated circuit chips are fabricated from a semiconductor wafer. Peripheral trenches are formed in the wafer which laterally delimit integrated circuit chips to be formed. A depth of the peripheral trenches is greater than or equal to a desired final thickness of the integrated circuit chips. The peripheral trenches are formed by a process which repeats successive steps of a) ion etching using a sulfur hexafluoride plasma, and b) passivating using an octafluorocyclobutane plasma. Upon completion of the step of forming the peripheral trenches, lateral walls of the peripheral trenches are covered by an insulating layer of a polyfluoroethene. A thinning step is performed on the lower surface of the wafer until a bottom of the peripheral trenches is reached. The insulating layer is not removed.