Lattice Array Memory With Enclosing Transistors
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Solution Overview
Problem
Conventional phase change memory arrays face limitations in providing sufficient programming current to phase change memory elements, leading to inefficiencies in transitioning between amorphous and crystalline states, and require complex trench isolation processes.
Innovation Solution
A phase change memory array with word lines configured in a lattice configuration, where transistors enclose the phase change memory elements, allowing for increased current delivery and optimizing silicon area usage by sharing source/drain regions, thereby simplifying the fabrication process without the need for trench isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional planar transistors are used in phase change memory arrays, then the fabrication process requires trench isolation, but the current drive capability is insufficient
Solution Approach 1:
The patent transitions from conventional planar transistor geometry to a vertically stacked three-dimensional transistor structure. This dimensional change enables multiple source/drain regions to be stacked above each other, significantly increasing current drive capability while eliminating the need for trench isolation in the lateral direction, thus simplifying the fabrication process.
2Reliability
If trench isolation processes are used, then transistor isolation is achieved, but fabrication complexity increases
Solution Approach 1:
The patent extracts and removes the trench isolation step from the fabrication process by using vertically stacked transistor structures with shared source/drain regions. This eliminates the need for complex lateral isolation trenches while maintaining proper transistor isolation through the vertical stacking architecture and selective gating.
3Power
If more silicon area is used per transistor, then current drive can be increased, but memory array density decreases
Solution Approach 1:
The patent merges multiple transistor functions into a single vertically stacked structure where source/drain regions are shared among adjacent transistors. This consolidation allows multiple transistors to share common current paths and regions, significantly increasing current drive capability while reducing the lateral silicon footprint and improving memory array density.
Solution Approach 2:
By moving from two-dimensional planar expansion to three-dimensional vertical stacking, the patent increases current drive capability through added vertical current paths without proportionally increasing lateral silicon area. The stacked architecture enables higher current density within the same footprint by utilizing the vertical dimension for additional current-carrying channels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration provides more than four times the current drive of conventional planar transistors, optimizes silicon area usage, and simplifies the fabrication process by eliminating the need for trench isolation, enhancing the efficiency and reliability of phase change memory arrays.
Implementation Method 1
Materials have been investigated for use in non-volatile memory cells. One class of programmable resistance materials are phase change materials, such as chalcogenide alloys, which are capable of stably transitioning between amorphous and crystalline phases.
Implementation Method 2
To obtain an amorphous state, a relatively high write current pulse (a reset pulse) is applied through the phase change memory element to melt at least a portion of the phase change material covering the first electrode
Data Source
AI summary
A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations.