Lattice-Matched Contact Plug and Seeding Layer for Semiconductor Devices

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As semiconductor devices scale down, the critical dimension of contacts decreases, leading to increased contact resistance and various defects, which existing technologies have not adequately addressed.

Innovation Solution

The semiconductor device incorporates a seeding layer with a first crystalline metal and a contact plug with a second crystalline metal, both having a similar crystal structure and lattice constants, to enhance bonding strength and reduce contact resistance, with the contact plug being lattice-matched to the seeding layer to increase grain size and lower resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the critical dimension of contact is scaled down to increase integration density, then device integration density is improved, but contact resistance increases and contact reliability deteriorates

Engineering Contradiction:
Improveintegration densityVSAvoidcontact reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The contact structure is segmented into multiple layers: a seeding layer and a contact plug layer. This segmentation allows each layer to be optimized for specific functions - the seeding layer for strong adhesion and crystal template provision, and the contact plug for low resistance and lattice matching, thereby resolving the contradiction between miniaturization and contact reliability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The contact structure uses composite materials with different crystalline properties. The seeding layer and contact plug are made of different crystalline metals that are lattice-matched, creating a composite structure that provides both strong bonding (from the seeding layer) and low contact resistance (from the lattice-matched contact plug), thus improving reliability while maintaining scaled dimensions

Inventive Principle:
Principle #40Composite materials

2Ease of manufacture

If conventional contact structures are used in scaled-down devices, then manufacturing process simplicity is maintained, but contact plug detachment and defects occur

Engineering Contradiction:
Improveprocess simplicityVSAvoidcontact stability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The seeding layer is formed in advance before the contact plug is deposited. This preliminary action creates a prepared surface with specific crystalline orientation and adhesion properties that prevent subsequent contact plug detachment and defects, while still using standard deposition processes

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The seeding layer acts as an intermediary between the substrate and the contact plug. It provides a crystalline template and adhesion interface that prevents direct bonding issues between the contact plug and underlying layers, thereby preventing detachment and defects without complicating the overall manufacturing process

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively prevents contact plug detachment during processing, significantly decreases contact resistance, and improves the reliability of semiconductor devices by ensuring strong bonding and low resistance.

Implementation Method 1

The second crystalline metal may be substantially lattice-matched to the first crystalline metal at an interface between the seeding layer and the contact plug

Methodology Applied
Scientific EffectLattice matching:

Data Source

PatentUS11631769B2Semiconductor device
Publication Date: 2023.04.18 SAMSUNG ELECTRONICS CO LTD
  • US11631769B2 patent drawing
  • US11631769B2 patent drawing
  • US11631769B2 patent drawing

AI summary

A semiconductor device includes: a fin-type active region extending on a substrate in a first direction; a gate structure extending across the fin-type active region in a second direction, different from the first direction; a source/drain region in the fin-type active region on one side of the gate structure; and first and second contact structures connected to the source/drain region and the gate structure, respectively, wherein at least one of the first and second contact structures includes a seeding layer on at least one of the gate structure and the source/drain region and including a first crystalline metal, and a contact plug on the seeding layer and including a second crystalline metal different from the first crystalline metal, and the second crystalline metal is substantially lattice-matched to the first crystalline metal at an interface between the seeding layer and the contact plug.