Configurable IC Launch-Capture Testing for Path Delay Precision
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Solution Overview
Problem
Traditional testing methods for configurable integrated circuits (ICs) fail to accurately measure performance due to aggregation of transistor and wire performance, leading to potential malfunctioning paths being overlooked, especially under high switching rates and varying user designs, and do not adequately account for power supply stress, temperature, and clock skew.
Innovation Solution
The launch-capture testing method breaks down long signal paths into smaller segments using configurable capture elements and launch elements, allowing for micro-granular testing of signal-path delay, power supply variation, and temperature measurement, while using multiple clock domains and phase-shifted clock signals to achieve precise delay measurements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional aggregate testing methods are used, then testing simplicity is maintained, but measurement precision deteriorates due to inability to detect individual slow transistors or wires
Solution Approach 1:
The patent segments the signal path into multiple smaller segments by inserting launch and capture elements at intermediate points between input and output. This allows measurement of delay in each segment individually rather than aggregating the entire path, enabling detection of slow transistors or wires in specific segments while maintaining overall test effectiveness.
2Productivity
If minimum width transistors are used to increase circuit density, then manufacturing precision is improved, but reliability deteriorates due to larger transistor-to-transistor variation and slower operation
Solution Approach 1:
The patent replaces traditional functional testing with a measurement-based approach using launch-capture elements. Instead of relying on aggregate functional behavior that may mask individual transistor failures, the system directly measures propagation delay through the circuit, substituting indirect functional testing with direct physical parameter measurement to identify performance variations.
3Speed
If high switching rates are used to improve performance, then speed increases, but temperature and power supply stress increase causing performance degradation
Solution Approach 1:
The patent performs delay measurements at various operating conditions including elevated temperature and power supply stress before final circuit operation. By characterizing circuit behavior under stressed conditions in advance, the system can compensate for performance degradation due to temperature and power variations during actual high-speed operation, ensuring reliable timing margins.
4Measurement precision
If traditional single-edge propagation testing is used, then test simplicity is maintained, but measurement precision deteriorates due to inability to capture multiple operational paths simultaneously
Solution Approach 1:
The patent merges multiple measurement capabilities into a single launch-capture test structure. By placing multiple capture elements along different signal paths and using a single launch element, the system can simultaneously measure delay across multiple operational paths in one test configuration, rather than requiring separate tests for each path.
Data Source
AI summary
A method for testing a set of circuitry in an integrated circuit (IC) is described. The IC includes multiple configurable circuits for configurably performing multiple operations. The method configures the IC to operate in a user mode with a set of test paths that satisfies a set of evaluation criteria. Each test path includes a controllable storage element for controllably storing a signal that the storage element receives. The method operates the IC in user mode. The method reads the values stored in the storage elements to determine whether the set of circuitry is operating within specified performance limits.