Launch Off Shift Module for SoC Transition Fault Testing
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Solution Overview
Problem
Existing launch off shift methodologies for transition fault testing in SoC designs face challenges such as difficulty in handling variations in shift-enable and clock polarities, leading to increased hardware requirements and synthesis run-time, as well as limitations in reusing combinational logic and inserting launch off shift modules in power-aware locations.
Innovation Solution
The implementation of an encapsulated launch off shift pipeline methodology that includes all possible variations of combinational logic, allows for the reuse of modules, and enables power-aware insertion of launch off shift modules, including clock and scan enable tap points, to minimize hardware overhead and synthesis time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing launch off shift methodologies are used to handle variations in shift-enable and clock polarities, then testing coverage is maintained, but hardware requirements increase and synthesis run-time increases
Solution Approach 1:
The patent creates a universal launch off shift module that can handle multiple polarity variations (positive/negative shift-enable and clock polarities) through a single standardized interface. The module internally adapts to different polarities using scan enable inversion logic and clock tree analysis, eliminating the need for separate modules for each polarity combination and reducing overall hardware complexity while maintaining full testing coverage
2Reliability
If existing launch off shift methodologies are used to handle variations in shift-enable and clock polarities, then testing coverage is maintained, but synthesis run-time increases
Solution Approach 1:
The patent performs clock tree analysis and identifies optimal tap points before module instantiation. By pre-determining the clock tree structure and selecting appropriate tap points in advance, the synthesis tool can quickly instantiate standardized modules without performing complex polarity analysis during synthesis, significantly reducing synthesis run-time while ensuring correct functionality
3Adaptability or versatility
If launch off shift modules are inserted without power domain awareness, then insertion flexibility is maintained, but power efficiency decreases
Solution Approach 1:
The patent implements power domain awareness by analyzing the power domain of the target flip-flop and selecting clock tap points from the same power domain. This ensures that launch off shift modules are inserted at locations that minimize power domain crossings and reduce dynamic power consumption, while the standardized module interface maintains insertion flexibility across different design points
Data Source
AI summary
Embodiments included herein are directed towards a launch off shift circuit module. Embodiments included a first flip-flop configured to receive a clock signal and a scan enable signal. Embodiments may further include a combinational logic circuit configured to receive an input from the first flip-flop and a launch off shift mode signal. The first flip-flop and the combinational logic circuit may be located inside a launch off shift module boundary.